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Scan sensing method that improves sensing marginsScan sensing method that improves sensing margins description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20090154260, Scan sensing method that improves sensing margins. Brief Patent Description - Full Patent Description - Patent Application Claims
This disclosure relates generally to systems for sensing memory devices and in particular, but not exclusively, relates to a scan sensing method that improves sensing margins. A wide variety of memory devices can be used to maintain and store data and instructions for various computers and similar systems, including non-volatile memory devices that do not require power to retain information (e.g., EPROM, EEPROM, and Flash memory). Memory devices contain memory cells, which store information in the form of binary bit(s) (e.g., logic “0”, “1”, “00”, “01”, “10”, or “11”). This information is retrieved by sensing the state of memory cells, e.g., by sensing current drawn by a memory cell and comparing such current with a reference current. For example, if the sensed current drawn by a memory cell exceeds a reference current, the memory cell\'s state is considered to be a logic 1; otherwise, the memory cell\'s state is considered to be a logic 0. One concern with sensing the state of a memory cell is reduced sensing margin. Improving sensing margin, which is the amount of sensed current/voltage above or below a fixed reference current/voltage, increases the usable lifetime of a memory cell. Sensing margin and the usable lifetime of a memory cell are reduced when a memory cell\'s characteristics (e.g., threshold voltage) change over time, affecting how data stored in the memory cell is evaluated. For example, if at the beginning of life of a memory cell, current sensed during a read operation of the memory cell exceeds a fixed reference current, the state of the memory cell is considered to be a logic 1. However, if after a period of time, current sensed during a read operation of the memory cell is below the fixed reference current (e.g., due to charge retention), the state of the memory cell is considered to be a logic 0. Dynamic tracking reference devices can be used to improve sensing margin by reflecting the degree that a memory cell\'s characteristics have changed over time. However, dynamic tracking reference device performance is limited because dynamic reference device characteristics can differ from memory cell device characteristics, e.g., the sensing margin of a dynamic tracking reference device can differ from the sensing margin of a memory cell. Further, although sensing margin can be improved by utilizing trim bits to reflect individual memory cell characteristics, the use of trim bits increases memory cell programming overhead involved in memory device manufacturing and testing, and increases memory device design complexity. It is therefore desirable to have systems and methods that improve memory cell sensing margins, reduce overhead involved in memory device manufacturing and testing, and reduce memory device design complexity. The claimed subject matter relates to systems and methods for improving memory cell sensing margins by utilizing an optimal reference stimulus. Conventional sensing techniques utilizing dynamic tracking reference devices are limited since characteristics of such devices can differ from those of memory cell devices. Further, conventional sensing techniques utilizing trim bits to account for memory cell characteristics are limited because such techniques increase memory cell programming overhead. Compared to traditional sensing methods, the novel scan sensing systems and methods of the claimed subject matter have various advantages. The usable lifetime of memory cells is increased because overall sensing margin is improved. Trim bit overhead and issues concerning the lack of sensitivity of static and dynamic tracking references to changes in memory cell characteristics are eliminated because the optimum reference stimulus is determined by sensing a memory cell characteristic as a function of the applied stimuli to determine an absolute minima point between distributions of a memory cell characteristic. The following presents a simplified summary of the innovation in order to provide a basic understanding of some aspects described herein. This summary is not an extensive overview of the disclosed subject matter. It is intended to neither identify key or critical elements of the disclosed subject matter nor delineate the scope of the subject innovation. Its sole purpose is to present some concepts of the disclosed subject matter in a simplified form as a prelude to the more detailed description that is presented later. The subject invention provides systems and methods that improve memory cell sensing margins by utilizing an optimal reference stimulus. In accordance with one aspect of the disclosed subject matter, a stimulus component can be employed to apply a plurality of different reference stimuli to a plurality of memory cells of a memory device. A sense component can be employed to sense a characteristic of each memory cell of the plurality of memory cells. An analysis component can be employed to compute an optimal reference stimulus by selecting one of the plurality of different reference stimuli, the one of the plurality of different reference stimuli associated with an absolute minima of number of memory cell characteristics that changed state as a function of the applied plurality of different reference stimuli. Further, the sense component can sense the characteristic of each memory cell of the plurality of memory cells as a function of the applied optimal reference stimulus. In one embodiment, the stimulus component can serially apply n different reference stimuli. The sense component can sense a characteristic of each memory cell as a function of the serially applied n different reference stimuli. A data store component can store the sensed characteristic of each memory cell. The analysis component can compute the optimal reference stimulus by selecting one of the serially applied n different reference stimuli, the one of the serially applied n different reference stimuli associated with an absolute minima of number of memory cell characteristics that changed state as a function of the serially applied n different reference stimuli. In another embodiment, the stimulus component comprises at least one of voltage or current. The sense component comprises one or more outputs of one or more window comparators, the one or more window comparators coupled to at least one memory cell of the plurality of memory cells. The analysis component computes the optimal reference stimulus by selecting a reference stimulus within a window region of one of the one or more window comparators, the least number of memory cells activating the one or more outputs of the one of the one or more window comparators. The following description and the annexed drawings set forth in detail certain illustrative aspects of the disclosed subject matter. These aspects are indicative, however, of but a few of the various ways in which the principles of the innovation may be employed. The disclosed subject matter is intended to include all such aspects and their equivalents. Other advantages and distinctive features of the disclosed subject matter will become apparent from the following detailed description of the innovation when considered in conjunction with the drawings. Non-limiting and non-exhaustive embodiments of the invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified. Continue reading about Scan sensing method that improves sensing margins... Full patent description for Scan sensing method that improves sensing margins Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Scan sensing method that improves sensing margins patent application. Patent Applications in related categories: 20090290437 - Circuit for and an electronic device including a nonvolatile memory cell and a process of forming the electronic device - A circuit for a nonvolatile memory cell can include a charge-altering terminal and an output terminal. The circuit can also include a first transistor having a gate electrode that electrically floats and an active region including a current-carrying electrode, wherein the current-carrying electrode is coupled to the output terminal. The ... 20090290438 - Semiconductor memory device including write selectors - A semiconductor memory device includes: static memory cells arranged in a matrix; a read bit line for transmitting data read from one of the memory cells; a write bit line for transmitting data to be written to one of the memory cells; an input data line for transmitting data which ... ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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