Semiconductor device

The Present application claims priority from Japanese application JP 2007-324991 filed on Dec. 17, 2007, the content of which is hereby incorporated by reference into this application.

1. Field of the Invention

The present invention relates to a semiconductor device including a plurality of circuits for performing predetermined processing to an inputted signal, and furthermore relates to a circuit technique for reducing amount of margin, which is secured when a circuit is designed in order to allow circuit operation even if performance of a manufactured integrated-circuit is varied, so that a semiconductor chip may operate with optimum performance of the circuit.

2. Description of the Related Art

With progress of size reduction in semiconductor manufacturing process, variation is increased in threshold voltage (Vth) of a MOS transistor. When Vth of a manufactured MOS transistor is decreased due to variation in Vth, since a drive current of the MOS transistor is increased, operable operation speed of a circuit is increased. Conversely, when Vth of a manufactured MOS transistor is increased due to variation in Vth, since a drive current of the MOS transistor is decreased, operable operation speed of a circuit is decreased. When processing size is decreased to less than 90 nm in the semiconductor manufacturing process, difference in speed caused by variation is increased due to increase in variation of Vth, leading to difficulty in determination of operation speed of a circuit. Particularly, in case of using a technique called FV control in which each of operation frequency and power voltage of a circuit is changed depending on required performance of the circuit, since operable frequency of the circuit is different depending on power voltage, when the circuit is designed, operation frequency is hardly determined to meet any power voltage depending on variation. Therefore, when optimum operation frequency can be determined by measuring a characteristic of a manufactured circuit, performance of the manufactured circuit can be adequately used. For example, JP-A-2003-273234 describes a technique where timing of a clock inputted into a circuit is controlled to measure performance of the circuit.

With progress of a manufacturing process of LSI (Large Scale Integrated circuit), a transistor in LSI is progressively reduced in size. For example, a small transistor having a transistor gate length of 50 nm was mass-produced in 2006. A transistor is progressively reduced in size, which increases variation in Vth of the transistor, consequently Vth of a transistor configuring an actually manufactured circuit is greatly shifted from Vth of the transistor when designed. For example, in case that Vth of a manufactured transistor is higher than Vth of the transistor when designed, operation current of the transistor decreases, leading to reduction in operation speed. Particularly, in case of using the FV control technique, a power voltage required for operation of a circuit at a predetermined frequency needs to be accurately measured for each manufactured circuit, and a result of the measurement needs to be held in the circuit.

In the JP-A-2003-273234, two memory flip flops (FF) are provided, which are disposed in a path called critical path being slowest in signal transfer, timing of a clock for controlling respective FF is shifted between the flip flops, and contents of data held in the respective FF are compared to each other, thereby whether timing error occurs is measured. In such a case, power voltage is gradually decreased, and in case that occurrence of error is found from a result of the comparison between the FF, the power voltage is increased, so that a lower limit value of the power voltage is measured. However, in the JP-A-2003-273234, output Sig106 of a determiner 106 is directly inputted into a power voltage control circuit, and power voltage is adjusted in accordance with error determination of the output Sig106. Therefore, (1) in case that noise such as a glitch occurs in Sig106, it may be determined as error determination, and consequently even if a power voltage can be essentially lowered, the voltage is possibly increased. In addition, (2) control is performed in a way that when error occurs, power voltage is increased, and when error does not occur, the power voltage is decreased as shown in FIG. 9. Therefore, in such control, power voltage fluctuates at any time. In the JP-A-2003-273234, what degree of pitch is used for changing the power voltage is not known. In case that the pitch is small, since a fluctuation area is small, any problem may not particularly occur. However, in case that the pitch is small, the power voltage hardly reaches the lower limit value unless the control is performed many times, therefore much time is possibly required for control. On the other hand, in case that the pitch is made large in order to fast reach the lower limit value, operation speed is greatly affected by the pitch, thereby stable operation of a circuit, being essentially intended, may not be performed. Moreover, in case that the lower limit value of power voltage is measured, if a prior state of a circuit is not kept in case that the power voltage is gradually changed, a minimum power voltage value above which no error occurs cannot be measured when timing error occurs. Furthermore, (3) a configuration is used, in which an arithmetic circuit group 203 performing normal operation outputs data for error determination, in addition, error determination is performed in each clock cycle. In case that error determination is performed in each clock cycle, data in F/F need to be inverted. Therefore, the technique is hard to be used for portions other than a portion where data outputted from a typical logic circuit unit is changed in logical value between “1” and “0” in each clock cycle. Finally, (4) when a circuit is designed, a path being slowest in signal transfer has been able to be estimated in the past. However, in a circuit manufactured by a current, fine semiconductor manufacturing process, since variation in Vth of a MOS transistor is increased, a plurality of paths (critical paths) being slowest in signal transfer are considered to exist, therefore a plurality of paths to be measured in timing are necessary. In JP-A-2003-273234, since F/F for error determination is additionally provided, if the technique is used for a plurality of paths, circuit scale is increased.

The foregoing and other objects and novel features of the invention will be clarified from description of the specification and accompanying drawings.

A typical invention among inventions disclosed in the application is briefly described as follows.

That is, a speed performance measurement circuit that may measure speed performance is provided between a first logic circuit and a second logic circuit. The speed performance measurement circuit includes a first flip flop that stores first data inputted in synchronization with a first clock signal, a first delay circuit that delays the first data and generates second data, a second flip flop that stores the second data inputted in synchronization with the first clock signal, a first comparator circuit that compares output of the first flip flop to output of the second flip flop, and a third flip flop that stores data of an output signal from the first comparator circuit in accordance with timing of the first clock signal. A measurement result of change in speed with respect to power voltage in a critical path is obtained from output of the third flip flop.

An advantage obtained by a typical invention among inventions disclosed in the application is briefly described as follows.

That is, change in speed with respect to power voltage in a critical path can be measured.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a circuit diagram of a configuration example of a major part of SOC as an example of a semiconductor device according to the invention;

FIG. 2 shows an operation timing chart of a major part of a circuit shown in FIG. 1;

FIG. 3 shows another operation timing chart of the major part of the circuit shown in FIG. 1;

FIG. 4 shows a block diagram of a configuration example of a major part of SOC as the example of the semiconductor device according to the invention;

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