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Multi-speed burst mode serializer/de-serializerMulti-speed burst mode serializer/de-serializer description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20090146852, Multi-speed burst mode serializer/de-serializer. Brief Patent Description - Full Patent Description - Patent Application Claims
1. Field of the Invention The present invention relates generally to a serializer/de-serializer (SerDes) and, more particularly, to a multi-speed burst mode SerDes. 2. Introduction A SerDes is an integrated circuit (IC or chip) transceiver that converts parallel data to serial data and vice-versa. The transmitter section has parallel data lines coming in and a serial output data stream. For example, a SerDes in a gigabit Ethernet system would include 10 parallel data lines that can be clocked at 125 Mhz, with the resulting serial output clocked at 1.25 Ghz. The gigabit Ethernet SerDes would commonly use an 8 B/10 B coding scheme that maps 8-bit symbols to 10-bit symbols to achieve DC-balance on the line. As would be appreciated, the receiver section is the reverse of the transmitter section and would have a serial data stream coming in with parallel data lines coming out. The receiver section would also recover the clock embedded in the received signal for use in the decoding process. In general, the PMA abstracts the PCS from the physical medium. Accordingly, the PCS can be unaware of whether the medium is copper or fiber. The primary functions of the PMA include mapping of transmit and receive code-groups between the PCS and PMA, serialization/de-serialization of code-groups for transmission/reception on the underlying serial PMD, recovery of clock from the coded data (e.g., 8 B/10 B, 64 B/66 B, etc.) supplied by the PMD, and mapping of transmit and receive bits between the PMA and PMD. The PMD is generally responsible for generating electrical or optical signals depending on the nature of the physical medium connected. PMD signals are sent to the medium dependent interface (MDI), which is the actual medium connected, including connectors, for the various media supported. As noted above, the PMA is responsible for the recovery of the received clock, which is used by the PCS to sample the data presented to it by the PMA. Conventional clock recovery mechanisms use delay locked loops (DLLs) or phase locked loops (PLLs) that align a local clock\'s phase to the phase of the recovered clock. For point-to-point systems, the locking to an incoming embedded clock is a one-time event prior to the communication of data across the link. For this reason, the process of locking to an incoming embedded clock need not be bounded by a particular locking time requirement. As would be appreciated, the relaxed timing requirement for locking to an incoming embedded clock can relax the design requirements of the SerDes. In a point-to-multipoint system such as an Ethernet passive optical network (EPON), a single optical line terminal (OLT) at a head end can be designed to communicate with a plurality of optical network units (ONTs) at various end nodes. This arrangement leverages a shared fiber optic plant by multiple networking nodes. Typically, the OLT broadcasts its transmissions in the downstream direction to all the ONTs. Each of the ONTs, on the other hand, transmit in the upstream direction to the OLT. It should be noted that the OLT and ONTs need not transmit at the same signaling rate or bandwidth. It should also be noted that the ONTs can be designed to share bandwidth or use a different wavelength in the upstream direction to eliminate overlap. In receiving a plurality of individual communications from the various connected ONTs, some of which may be transmitting at different rates, the SerDes in the OLT is required to acquire phase and frequency for each of the individual ONT communications. What is needed therefore is a SerDes design that can operate in a multi-speed burst mode. A multi-speed burst mode serializer/de-serializer, substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims. In order to describe the manner in which the above-recited and other advantages and features of the invention can be obtained, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. Understanding that these drawings depict only typical embodiments of the invention and are not therefore to be considered limiting of its scope, the invention will be described and explained with additional specificity and detail through the use of the accompanying drawings in which: Continue reading about Multi-speed burst mode serializer/de-serializer... Full patent description for Multi-speed burst mode serializer/de-serializer Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Multi-speed burst mode serializer/de-serializer patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Multi-speed burst mode serializer/de-serializer or other areas of interest. ### Previous Patent Application: N-state ripple adder scheme coding with corresponding n-state ripple adder scheme decoding Next Patent Application: Scalable context adaptive binary arithmetic coding Industry Class: Coded data generation or conversion ### FreshPatents.com Support Thank you for viewing the Multi-speed burst mode serializer/de-serializer patent info. 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