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06/11/09 - USPTO Class 257 |  106 views | #20090146298 | Prev - Next | About this Page  257 rss/xml feed  monitor keywords

Semiconductor device having solder-free gold bump contacts for stability in repeated temperature cycles

USPTO Application #: 20090146298
Title: Semiconductor device having solder-free gold bump contacts for stability in repeated temperature cycles
Abstract: A semiconductor device has a chip (101) with gold studs (212) assembled on a tape substrate (102), which has solder balls (103) for attachment to external parts. The tape substrate (about 30 to 70 μm thick) has on its first surface first copper contact pads (221) covered with a continuous thin nickel layer (222) of about 0.04 to 0.12 μm thickness. Gold including stud (212) is contacting the nickel. On the second substrate surface are second copper contact pads (231) covered with an alloy layer (about 2 to 3 μm thick) including gold, copper/tin alloys, and copper/nickel/tin alloys; the alloys are metallurgically attached to the second copper pad and substantially free of unalloyed nickel. A reflow body (103) comprising tin is metallurgically attached to the alloy layer of each second pad. (end of abstract)



Agent: Texas Instruments Incorporated - Dallas, TX, US
Inventor: Mutsumi Masumoto
USPTO Applicaton #: 20090146298 - Class: 257737 (USPTO)

Semiconductor device having solder-free gold bump contacts for stability in repeated temperature cycles description/claims


The Patent Description & Claims data below is from USPTO Patent Application 20090146298, Semiconductor device having solder-free gold bump contacts for stability in repeated temperature cycles.

Brief Patent Description - Full Patent Description - Patent Application Claims
  monitor keywords FIELD OF THE INVENTION

The present invention is related in general to the field of semiconductor devices and processes, and more specifically to metallurgical systems for stable gold bump connections with and without solder.

DESCRIPTION OF RELATED ART

The growing popularity of flip-chip assembly in the fabrication process flow of silicon integrated circuit (IC) devices is driven by several facts. First, the electrical performance of the semiconductor devices can be improved when the parasitic inductances correlated with conventional wire bonding interconnection techniques are reduced. Second, flip-chip assembly provides higher interconnection densities between chip and package than wire bonding. Third, flip-chip assembly consumes less silicon “real estate” than wire bonding, and thus helps to conserve silicon area and reduce device cost. And fourth, the fabrication cost can be reduced, when concurrent gang-bonding techniques are employed rather than consecutive individual bonding steps.

In order to reduce bump size and bump pitch, efforts were undertaken to replace the earlier solder-based interconnecting balls with gold bumps, especially by an effort to create gold bumps by a modified wire ball technique. Typically, the gold bumps are created on an aluminum layer of the contact pads of semiconductor chips. Subsequently, the chips are attached to substrates using solder.

For many contemporary products, such as wireless telephones, the substrates with the attached chips have to be assembled on printed circuits or motherboards, and subsequently have to be tested in temperature cycles from ambient temperature to significantly elevated temperatures. For solder of pure tin or tin alloys, without lead, temperatures as high as 280° C. may be involved. It has been found routinely that solder-attached gold bumps fare poorly in these temperature excursions; the electrical resistance of the gold-solder contacts increases rapidly, or the gold bump dissolves in the molten solder alloy, or the contacts open altogether after only three or four temperature cycles.

SUMMARY OF THE INVENTION

Applicant conducted a metallurgical and statistical investigation of gold bump contact structures, with and without solder. The investigation discovered that gold bumps can be attached to gold layers over copper contacts without solder, when ultrasonic energy is employed and the support of a thin nickel layer between gold and copper is enlisted.

Extensive life tests further found that these gold-on-copper contacts exhibit only few percent (about 5 to 9%) changes in electrical resistance after ten or more temperature cycles up to the melting temperature (about 260° C.) of lead-free tin alloys, compared to the resistance right after the chip assembly. This result contrasts favorably with conventional life test results, which typically show a 5 to 10 fold increase of contact resistance or frequently a complete loss of contact (electrical open). In the analysis of the gold contacts, applicant discovered that the nickel layer diffused only slightly into the adjoining regions of gold and copper, and showed no change after device storage at 150° C. for 1000 hours.

One embodiment of the invention is a semiconductor device with a chip with gold studs, which is assembled on a tape substrate with solder balls for attachment to external parts. The tape substrate (about 30 to 70 μm thick) has on its first surface first copper contact pads covered with a continuous thin nickel layer of about 0.04 to 0.12 μm thickness. Gold including the stud is contacting the nickel. On the second substrate surface are second copper contact pads covered with an alloy layer (about 2 to 3 μm thick) including gold, copper/tin alloys, and copper/nickel/tin alloys; the alloys are metallurgically attached to the second copper pad and substantially free of unalloyed nickel. A reflow body comprising tin is metallurgically attached to the alloy layer of each second pad.

Another embodiment of the invention a method for assembling a semiconductor device with a chip with gold studs. A tape is provided with copper contact pads on the first and the second surface. The copper pads on both surfaces have a thin nickel layer (identical thickness about 0.04 to 0.12 μm) over the copper and a gold layer over the nickel; the contact locations on one tape surface match the chip gold studs. The tape is put into a frame to maintain flatness; the frame is then loaded on a machine with a surface to support the flat tape. The chip gold studs are pressed onto the matching gold layers of the first surface contacts, and ultrasonic energy with suitable amplitude, time, and temperature is applied to create gold-to-gold interdiffusion contact without breaking the nickel layer. Solder bodies are then attached to the contacts of the second surface; in the reflow process, an alloy layer is created including gold, copper/tin alloys, and copper nickel/tin alloys substantially free of unalloyed nickel. The spaces between the studs attached to the substrate may be filled with a polymeric precursor, and the assembled chip and the first substrate surface may be covered with an encapsulation compound forming the package for the device.

The technical advances represented by certain embodiments of the invention will become apparent from the following description of the preferred embodiments of the invention, when considered in conjunction with the accompanying drawings and the novel features set forth in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a schematic cross section of a packaged semiconductor device with a substrate according to the invention.

FIG. 2 illustrates a portion of the device of FIG. 1, magnifying the layered structure of a substrate copper contact pad, which is contacted by the gold stud of the semiconductor chip.

FIG. 3 depicts the parts used for the assembly of the device portion in FIG. 2, illustrating the layered structure of the copper contact pads on both surfaces of the substrate.

FIG. 4 shows an example of the performance data of devices manufactured according to the invention compared to devices manufactured with conventional methods, the data plotting the resistance of the chip studs assembled on the substrate as a function of repeated temperature cycles as encountered during solder reflow in product assembly.



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