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06/04/09 - USPTO Class 713 |  38 views | #20090144564 | Prev - Next | About this Page  713 rss/xml feed  monitor keywords

Data encryption interface for reducing encrypt latency impact on standard traffic

USPTO Application #: 20090144564
Title: Data encryption interface for reducing encrypt latency impact on standard traffic
Abstract: Methods and apparatus that may be utilized in systems to reduce the impact of latency associated with encrypting data on non-encrypted data are provided. Secure and non-secure data may be routed independently. Thus, non-secure data may be forwarded on (e.g., to targeted write buffers), without waiting for previously sent secure data to be encrypted. As a result, non-secure data may be made available for subsequent processing much earlier than in conventional systems utilizing a common data path for both secure and non-secure data. (end of abstract)



USPTO Applicaton #: 20090144564 - Class: 713193 (USPTO)

Data encryption interface for reducing encrypt latency impact on standard traffic description/claims


The Patent Description & Claims data below is from USPTO Patent Application 20090144564, Data encryption interface for reducing encrypt latency impact on standard traffic.

Brief Patent Description - Full Patent Description - Patent Application Claims
  monitor keywords CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of co-pending U.S. patent application Ser. No. 10/932,943, filed Sep. 2, 2004, which is herein incorporated by reference in its entirety.

This application is related to commonly assigned co-pending application entitled “Low-Latency Data Decryption Interface” (Atty. Docket No. ROC920040013), filed herewith and hereby incorporated by reference in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to data encryption and, more particularly, to methods and apparatus for reducing latency associated with selectively encrypting portions of data.

2. Description of the Related Art

A system on a chip (SOC) generally includes one or more integrated processor cores, some type of embedded memory, such as a cache memory, and peripheral interfaces, such as memory control components and external bus interfaces, on a single chip to form a complete (or nearly complete) system.

As part of an enhanced security feature, some SOCs encrypt some portions of data prior to storing it in external memory. Adding such encryption to an SOC may add valuable benefits, such as preventing a hacker from obtaining instructions of a copyrighted program, such as a video game, or data that may be used to determine such instructions through reverse engineering. However, adding encryption typically impacts system performance, as conventional encryption schemes typically stream both data that is to be encrypted and data that is not to be encrypted (non-encrypted data) through a common sequential data path. As a result, non-encrypted data is typically suffers the same latency as encrypted data.

This latency may add significant delay to the storing of non-encrypted data. In addition, this latency may prevent the subsequent storage of non-encrypted data while previous data is being encrypted. Accordingly, what is needed is a mechanism to minimize performance impacts on non-encrypted data caused by encryption latency.

SUMMARY OF THE INVENTION

The present invention generally provides a method and apparatus that can improve the performance of systems with encrypted memory regions while ensuring that encrypted and non-encrypted data are correctly written to their respective memory locations.

BRIEF DESCRIPTION OF THE DRAWINGS

So that the manner in which the above recited features, advantages and objects of the present invention are attained and can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to the embodiments thereof which are illustrated in the appended drawings.

It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.

FIG. 1 illustrates an exemplary system including a central processing unit (CPU), in which embodiments of the present invention may be utilized.

FIG. 2 is a block diagram of components of the CPU, according to one embodiment of the present invention.

FIG. 3 is a block diagram of the encryption data path of the CPU, according to one embodiment of the present invention.



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Method and system for software protection using binary encoding
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Industry Class:
Electrical computers and digital processing systems: support

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