Reception device

The present invention relates to a reception device in a wired or wireless transmission system adopting a multicarrier transmission system, and in particular to a reception device capable of correcting a carrier frequency error and a clock frequency error.

Recently, a multicarrier transmission system is a center of attention as a transmission system of digital signals. The multicarrier transmission system is a modulation system of serial/parallel-converting data to be transmitted to lower the symbol rate and then assigning data to an amplitude and a phase of a plurality of sub bands which are orthogonal to each other, so as to transmit the data. The multicarrier transmission system divides a transmission band into a plurality of sub bands for transmitting data. Accordingly, the multicarrier transmission system can vary the modulation system for each sub band, and therefore can flexibly use the frequency. The multicarrier transmission system also lowers the symbol rate, and therefore increases the resistance against the delay wave. For these reasons, the multicarrier transmission system is strong against multipath disturbance.

As a multicarrier transmission system, OFDM (orthogonal frequency division multiplexing), wavelet modulation using an orthogonal wavelet function, and the like have been proposed.

FIG. 10 shows a structure of a conventional OFDM reception device 210 disclosed in patent document 1. As shown in FIG. 10, the OFDM reception device 210 includes an A/D converter 201, a clock generation circuit 202, a complex multiplication circuit 203, a guard correlation calculation circuit 204, a numerical controlled oscillator (NCO) 205, a fast Fourier transform circuit 206, a carrier frequency error calculation circuit 207, a clock frequency reproduction circuit 208, and a data demodulation unit 209.

The A/D converter 201 samples a received signal and converts the received signal into a digital signal, based on a clock which is input from the clock generation circuit 202.

The complex multiplication circuit 203 multiples a complex sine wave signal which is input from the NCO 205 by the received signal converted into the digital signal, and corrects a frequency error.

The frequency error is first roughly estimated by the guard correlation calculation circuit 204. In order to increase the resistance against the delay wave, an OFDM signal includes a guard interval cyclically repeated in an OFDM symbol. The guard correlation calculation circuit 204 calculates a correlation value between an input OFDM signal and an OFDM signal delayed by an effective symbol time. The guard correlation calculation circuit 204 obtains a timing at which the correlation is peaked and a phase of the OFDM signal at that timing. Based on the obtained phase, the guard correlation calculation circuit 204 obtains a phase difference at an effective symbol time interval. The phase difference corresponds to the frequency error. Accordingly, the guard correlation calculation circuit 204 controls the NCO 205 so as to counteract the frequency error.

The timing at which the correlation is peaked represents an effective symbol interval. Based on the timing, the fast Fourier transform circuit 206 transforms an OFDM signal, having a rough frequency thereof corrected, into a signal in the frequency range, and outputs an amplitude and a phase of each of sub bands. The data demodulation unit 209 demodulates data of each sub band based on such an amplitude and phase.

An OFDM signal has a pilot signal, assigned a predetermined phase and amplitude, inserted into a predetermined sub band. In a conventional OFDM reception device, frequency error correction, equalization and the like are performed based on such a pilot signal.

The carrier frequency error calculation circuit 207 extracts only a predetermined pilot signal based on information on each sub band which is output from the fast Fourier transform circuit 206. The carrier frequency error calculation circuit 207 estimates a residual frequency error based on a phase change of the predetermined pilot signal. The carrier frequency error calculation circuit 207 controls the NCO 205 based on the residual frequency error. Thus, more precise carrier frequency synchronization is performed.

The clock frequency reproduction circuit 208 estimates a clock frequency error based on the phase change of the pilot signal. The clock frequency reproduction circuit 208 controls the clock generation circuit 202 based on the clock frequency error. Thus, the clock frequency error is corrected.

Patent Document 1: Japanese Laid-Open Patent Publication No. 10-308715

However, the above-described conventional structure needs to use the fast Fourier transform calculation circuit 206 in order to estimate a clock frequency error. The transform processing performed by the fast Fourier transform calculation circuit 206 requires a certain amount of time. Therefore, the conventional structure has a problem that a certain amount of time is necessary until the clock frequency control loop is converged.

With OFDM, when the carrier frequency error is large, sub bands may occasionally not be orthogonal to each other. This causes interference among the sub bands. As a result, there occurs a problem that the pilot signal cannot be accurately extracted even by Fourier transform. With the conventional structure, the rough frequency error is corrected using the guard interval correlation. However, in the case where the phase difference at the effective symbol time interval is used, only a frequency error of the sub band interval or smaller can be estimated. Therefore, for a frequency error larger than the sub band interval, a synchronization symbol for frequency error estimation needs to be additionally used.

With OFDM, rough frequency error estimation and effective symbol timing estimation can be performed using the guard interval correlation. However, with a modulation system which does not use the guard interval, such as wavelet modulation for performing multicarrier modulation using an orthogonal wavelet function or the like, it is necessary to especially use a synchronization symbol for performing frequency error estimation and effective symbol timing estimation.

Therefore, an object of the present invention is to provide a reception device capable of performing symbol timing estimation, carrier frequency error estimation, and clock frequency error estimation in a short period of time even when the carrier frequency error is large.

To achieve the above objects, the present invention has the following aspects. A first aspect of the present invention is directed to a reception device for receiving a transmission frame including a synchronization symbol string, having a synchronization symbol repeated a plurality of times, inserted before a data symbol string. The synchronization symbol is a symbol obtained by synthesizing a plurality of sub band symbols which are orthogonal to each other and having different carrier frequencies. The carrier frequencies of the plurality of sub band symbols are located at an equal predetermined frequency interval. The synchronization symbol includes a synchronization pattern repeated at an interval of a reciprocal of the predetermined frequency interval. The reception device comprises a clock generation unit for generating a sampling clock; an analog/digital converter for sampling the transmission frame based on the sampling clock generated by the clock generation unit and analog/digital-converting the transmission frame; a frequency correction unit for correcting a frequency of an output from the analog/digital converter; a synchronization pattern correlation unit for obtaining a correlation between the output from the frequency correction unit and the synchronization pattern, and outputting the correlation as a synchronization pattern correlation value; a peak detection unit for detecting a peak of the output from the synchronization pattern correlation unit, and outputting the peak as a peak timing; a timing determination unit for outputting a predetermined timing in the synchronization symbol based on the peak timing which is output from the peak detection unit; an inter-synchronization pattern phase difference detection unit for detecting a change amount of a phase of the synchronization pattern correlation value which is output from the synchronization pattern correlation unit in accordance with the output from the timing determination unit and the peak timing which is output from the peak detection unit, and estimating an error of the frequency of the output from the analog/digital converter based on the change amount of the phase of the synchronization pattern correlation value; a plurality of sub band correlation units each for obtaining a correlation between a sub band symbol assigned thereto, among the plurality of sub band symbols, and the output from the frequency correction unit, and outputting the correlation as a sub band correlation; an inter-symbol phase difference detection unit for obtaining a phase difference at a predetermined symbol interval of the sub band correlation which is output from each of the plurality of sub band correlation units in accordance with the output from the timing determination unit, outputting the phase difference as an inter-symbol phase difference, and estimating an error of the frequency of the output from the analog/digital converter based on the inter-symbol phase difference; an inter-sub band phase difference detection unit for detecting a phase difference, among the sub bands, of the inter-symbol phase difference which is output from the inter-symbol phase difference detection unit as an inter-sub band phase difference in accordance with the output from the timing determination unit, and estimating an error of the sampling clock based on the detected inter-sub band phase difference; and a data demodulation unit for demodulating the output from the frequency correction unit in accordance with the output from the timing determination unit. The frequency correction unit corrects the frequency of the output from the analog/digital converter based on the frequency error estimated by the inter-synchronization pattern phase difference detection unit, and then corrects the frequency of the output from the analog/digital converter based on the frequency error estimated by the inter-symbol phase difference detection unit. The clock generation unit corrects a frequency of the sampling clock based on the error estimated by the inter-sub band phase difference detection unit.

Preferably, the timing determination unit may output a start timing of the synchronization symbol string when the peak timing which is output from the peak detection unit is detected at the synchronization pattern interval a predetermined number of times, and output a termination timing of the synchronization symbol string when the peak timing stops being detected at the synchronization pattern interval.