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05/28/09 - USPTO Class 712 |  90 views | #20090138681 | Prev - Next | About this Page  712 rss/xml feed  monitor keywords

Synchronization of parallel processes

USPTO Application #: 20090138681
Title: Synchronization of parallel processes
Abstract: A speculative execution capability of a processor is exposed to program control through at least one machine instruction. The at least one machine instruction may be two instructions designed to facilitate synchronization between parallel processes. According to an aspect, an instruction set architecture includes circuitry that handles a speculative execution instruction and a speculation termination instruction. The speculative execution instruction may be an instruction that takes first and second operands, causes the processor to speculatively execute additional instructions if a memory location contains a value, and causes the processor to start executing instructions from an address indicated by the second operand if a mis-speculation occurs, and the speculation termination instruction may be an instruction that causes the processor to begin retiring the additional instructions. (end of abstract)



Agent: Fish & Richardson, PC - Minneapolis, MN, US
Inventor: Bratin Saha
USPTO Applicaton #: 20090138681 - Class: 712216 (USPTO)

Synchronization of parallel processes description/claims


The Patent Description & Claims data below is from USPTO Patent Application 20090138681, Synchronization of parallel processes.

Brief Patent Description - Full Patent Description - Patent Application Claims
  monitor keywords CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation application of and claims the benefit of priority to U.S. application Ser. No. 10/797,886, filed Mar. 9, 2004; the disclosure of the prior application is considered part of (and is incorporated by reference in) the disclosure of this application.

BACKGROUND

The present disclosure describes systems and techniques relating to program flow control, for example, synchronizing parallel processes.

A process is an executing software program, which may or may not share resources with other processes. Parallel processes are two or more processes that operate together in a computing system (e.g., parallel threads of a program) and share at least one system resource that may not be accessible by all the parallel processes together (e.g., a shared memory resource that may be corrupted if accessed in parallel by multiple processes). Access to such shared resources frequently needs to be synchronized, and this is typically done by placing shared-resource-access operations in a critical section of a program.

A critical section of a program may enforce serialized access to a shared resource among parallel processes. Traditionally this has been done using some form of atomic operation. An atomic operation is multiple sub-operations on a resource (e.g., read, modify and then write to a memory location) that the processor architecture forces to be performed together by not allowing multiple processes to overlap their performance of the multiple sub-operations. For example, an atomic read-modify-write instruction may be provided for use with a lock variable for a critical section; or support for a semaphore may be provided for use in controlling how many parallel processes can access a critical section. Thus, the processor architecture enables a simple shared resource to be made into a protected resource (e.g., a protected variable), which must be shared sequentially because of the processor architecture itself, allowing programmers to synchronize access to any number, and type of shared resources.

DRAWING DESCRIPTIONS

FIG. 1 illustrates synchronization of parallel processes.

FIG. 2 illustrates synchronization of parallel processes using processor speculation and cache coherence maintenance.

FIG. 3 is a block diagram illustrating a data processing machine.

FIG. 4 is a block diagram illustrating a system including a multiprocessor.

FIG. 5 illustrates an example code section implementing synchronization.

FIG. 6 illustrates a reorder buffer as may be used in a processor that supports a speculative execution instruction and a speculation termination instruction.

Details of one or more embodiments are set forth in the accompanying drawings and the description below. Other features and advantages may be apparent from the description and drawings, and from the claims.

DETAILED DESCRIPTION

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Previous Patent Application:
Vector atomic memory operations
Next Patent Application:
Dynamic instruction execution based on transaction priority tagging
Industry Class:
Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors)

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