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05/28/09 - USPTO Class 438 |  1 views | #20090137067 | Prev - Next | About this Page  438 rss/xml feed  monitor keywords

Method for forming an inductor

USPTO Application #: 20090137067
Title: Method for forming an inductor
Abstract: A spiral inductor fabricated above a semiconductor substrate provides a large inductance while occupying only a small surface area. Including a layer of magnetic material above and below the inductor increases the inductance of the inductor. The magnetic material also acts as barrier that confines electronic noise generated in the spiral inductor to the area occupied by the spiral inductor. Inductance in a pair of stacked spiral inductors is increased by including a layer of magnetic material between the stacked spiral inductors. (end of abstract)



Agent: Schwegman, Lundberg & Woessner/micron - Minneapolis, MN, US
Inventors: Leonard Forbes, Kie Y. Ahn
USPTO Applicaton #: 20090137067 - Class: 438 3 (USPTO)

Method for forming an inductor description/claims


The Patent Description & Claims data below is from USPTO Patent Application 20090137067, Method for forming an inductor.

Brief Patent Description - Full Patent Description - Patent Application Claims
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This application is a divisional of U.S. Patent Application Ser.. No. 09/946,054, filed Sep. 4, 2001, which is a continuation of U.S. Patent Application Ser. No. 09/789,146, filed Feb. 20, 2001, now U.S. Pat. No. 6,287,932, which is a divisional of U.S. Patent Application Ser. No. 09/243,584, filed Feb. 3, 1999, now U.S. Pat. No. 6,191,468, all of which are incorporated herein by reference in their entirety.

FIELD OF TECHNOLOGY

The present subject matter relates to inductors, and particularly to inductors used in integrated circuits.

BACKGROUND

The telecommunications and computer industries are driving the demand for miniaturized analog and mixed signal circuits. Inductors are a critical component in the traditional discrete element circuits, such as impedance matching circuits, resonant tank circuits, linear filters, and power circuits, used in these industries. Since traditional inductors are bulky components, successful integration of the traditional discrete element circuits requires the development of miniaturized inductors.

One approach to miniaturizing an inductor is to use standard integrated circuit building blocks, such as resistors, capacitors, and active circuitry, such as operational amplifiers, to design an active inductor that simulates the electrical properties of a discrete inductor. Active inductors can be designed to have a high inductance and a high Q factor, but inductors fabricated using these designs consume a great deal of power and generate noise.

A second approach to miniaturizing an inductor is to fabricate a solenoid type inductor with a core using conventional integrated circuit manufacturing process technology. Unfortunately, conventional integrated circuit process steps do not lend themselves to precisely and inexpensively fabricating a helical structure with a core. So, integrated circuit process technology is only marginally compatible with manufacturing a solenoid type inductor.

A third approach, sometimes used in the fabrication of miniature inductors in gallium arsenide circuits, is to fabricate a spiral type inductor using conventional integrated circuit processes. Unfortunately, this approach has a high cost factor associated with it when applied to fabricating inductors for use in silicon integrated circuits. Silicon integrated circuits operate at lower frequencies than gallium arsenide circuits, and generally require inductors having a higher inductance than inductors used in gallium arsenide circuits. The higher inductance is realized in a spiral inductor occupying a large surface area on the silicon substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a cross-sectional view of one embodiment of a square spiral inductor embedded in a solid state structure.

FIG. 1B is a top view of one embodiment of a square spiral inductor pattern.

FIG. 2 is a cross-sectional view one embodiment of an inductor coupled to another electronic device in an integrated circuit.

FIG. 3A is a cross-sectional view of one embodiment of two vertically stacked inductors.

FIG. 3B is a cross-sectional view of one embodiment of two stacked and serially connected inductors showing the current in the inductors and the resulting magnetic field lines.



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