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05/21/09 - USPTO Class 386 |  1 views | #20090129744 | Prev - Next | About this Page  386 rss/xml feed  monitor keywords

Video processing apparatus, method, and storage medium

USPTO Application #: 20090129744
Title: Video processing apparatus, method, and storage medium
Abstract: A video processing apparatus includes a packet generation unit configured to receive a frame of video data, to divide the frame into tiles, and to packetize each of the tiles, a setting unit configured to set a processing time of each packet generated by the packet generation unit, a processing unit configured to perform image processing on each packet, a measurement unit configured to measure a processing time of the image processing performed by the processing unit, a determination unit configured to determine a processing speed of the processing unit based on a result of comparison between the processing time of each packet set by the setting unit and the processing time measured by the measurement unit, and an output unit configured to combine the packets processed by the processing unit to output video data. (end of abstract)



Agent: Canon U.s.a. Inc. Intellectual Property Division - Irvine, CA, US
Inventor: Takeshi Furukawa
USPTO Applicaton #: 20090129744 - Class: 386 83 (USPTO)

Video processing apparatus, method, and storage medium description/claims


The Patent Description & Claims data below is from USPTO Patent Application 20090129744, Video processing apparatus, method, and storage medium.

Brief Patent Description - Full Patent Description - Patent Application Claims
  monitor keywords BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a video processing apparatus which executes image processing, more specifically, image processing of an image for each tile and a video processing method.

2. Description of the Related Art

Generally, in a video processing system, a video output unit such as a display needs to output synchronized video image and audio data. That is, the video output unit must synchronize the output timing of a video image and audio to coincide with each other.

In order to allow a video image and audio to be synchronized, Moving Picture Experts Group Phase 1 (MPEG-1) and Moving Picture Experts Group Phase 2 (MPEG-2), which are an international standard coding system, add a time stamp, which indicates timing information, to a packet header.

FIG. 9 illustrates a prior art block diagram of a conventional video processing system. The video processing system includes a packet transmission apparatus 9200 and a packet receiving apparatus 9300.

The packet transmission apparatus 9200 includes a video packet generation circuit 9201 and a system time clock generation circuit 9202. The video packet generation circuit 9201 receives video data from a video input apparatus 9100 and packetizes the video data to be transmitted. At this time, the video packet generation circuit 9201 generates a time stamp based on a time indicated by the system time clock generation circuit 9202 and adds the time stamp to a packet header.

The packet receiving apparatus 9300 receives the packet transmitted by the packet transmission apparatus 9200 via a packet transmission path 9500.

The packet receiving apparatus 9300 includes a video data transmission circuit 9301 and a system time clock reproduction circuit 9302. The video data transmission circuit 9301 receives the packet. When a time indicated by the system time clock reproduction circuit 9302 and a time indicated by the time stamp added to the packet header coincide with each other, the video data transmission circuit 9301 restores video data to transmit it to a video output apparatus 9400.

The time from when the packet transmission apparatus 9200 transmits a packet to when the packet receiving apparatus 9300 receives the packet is constant according to a system. Thus, a time stamp can be generated based on the system time clock generation circuit 9202.

In a conventional video processing system, the time from when a packet transmission apparatus transmits a packet to when a packet receiving apparatus receives the packet is constant according to a system. Therefore, the packet arrives at the packet receiving apparatus at a time indicated by a time stamp.

However, if a packet processing apparatus, which performs, for example, high quality processing, is provided between the packet transmission apparatus and the packet receiving apparatus, a packet may not arrive at the packet receiving apparatus at a time indicated by a time stamp. That is, when the packet processing apparatus accesses an external memory or the like, processing capability of the packet processing apparatus may significantly be reduced due to congestion of access and the packet may not arrive at an estimated time. Accordingly, video data cannot be output at a time indicated by a time stamp. This may cause a disturbance in a video image.

SUMMARY OF THE INVENTION

An exemplary embodiment of the present invention is directed to a video processing apparatus capable of reducing a disturbance in an image due to arrival delay of a packet.

According to an aspect of the present invention, a video processing apparatus includes a packet generation unit configured to receive a frame of video data, to divide the frame into tiles, and to packetize each of the tiles, a setting unit configured to set a processing time of each packet generated by the packet generation unit, a processing unit configured to perform image processing on each packet, a measurement unit configured to measure a processing time of the image processing performed by the processing unit, a determination unit configured to determine a processing speed of the processing unit based on a result of comparison between the processing time of each packet set by the setting unit and the processing time measured by the measurement unit, and an output unit configured to combine the packets processed by the processing unit to output video data.

According to an exemplary embodiment of the present invention, a disturbance in an image due to an arrival delay of a packet can be reduced.

Further features and aspects of the present invention will become apparent from the following detailed description of exemplary embodiments with reference to the attached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the invention and, together with the description, serve to explain the principles of the invention.



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