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Dynamically scalable queues for performance driven pci express memory trafficDynamically scalable queues for performance driven pci express memory traffic description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20090125666, Dynamically scalable queues for performance driven pci express memory traffic. Brief Patent Description - Full Patent Description - Patent Application Claims
The present application is a continuation of U.S. patent application Ser. No. 11/466,142, filed Aug. 22, 2006 and titled Dynamically Scalable Queues For Performance Driven PCI Express Memory Traffic, the contents of which is incorporated herein by reference. 1. Technical Field The present invention relates generally to computer systems and in particular to input/output operations of computer systems. Still more particularly, the present invention relates to an enhanced method and system for transferring input/output (IO) data from an IO device of a computer system. 2. Description of the Related Art Connections of Input/Output (IO) devices to computer systems and the associated transfer of data to and from the connected computer system are typically supported by one of several available hardware devices and associated protocols. In most conventional computer systems, the transfer protocol utilized for local interconnection of these IO devices is Peripheral Component Interconnect (PCI) Express. PCI Express (supported by specific hardware) is an implementation of the PCI computer bus that enables faster physical layer communications via use of a network of serial interconnects (in lieu of a single bus). PCI Express utilizes a single hub with many pins on the mainboard to enable switching and parallel data transfers. The higher speeds accomplished by PCI Express has enabled PCI express to become the new backplane standard in a majority of personal computers. This is also due in part to PCI Express\' design, which enables PCI Express to be completely transparent to software developers. Thus, an operating system designed for PCI is able to boot in a PCI Express system without any code modification. Conventional methods for enabling IO data transfer include the utilization of IO queues. However, developing queues for IO devices is currently application specific, particularly when transferring data via PCI Express. PCI Express utilizes a variable size packet-driven serial protocol to transfer data. A queuing structure is required to execute these transfers in a coherent manner. These IO queues are statically configured and support only a single type of data transfer well. For example, if the IO devices that drive the traffic are varied in (1) the sizes of transfers and/or (2) the number of outstanding transactions on the link, developing the queues becomes a choice of exclusively supporting (a) many large transfers, (b) a few large transfers, (c) many small transfers, or (d) a few small transfers. Each category of data transfer operates best at a particular (single) type of queue configuration and losses operational quality for all other types of transfers and corresponding queue configurations. The determination of which queue configuration works best for the particular IO transfer depends on what the computer system (or executing application) requests/requires. Thus, when the system/application is concurrently or sequentially providing different combinations of sizes and numbers of transactions, the statically-configured IO queues are unable to deliver high performance on all of the various configurations. The present invention recognizes and corrects this limitation in the existing IO data transfer methods, particularly those that utilize PCI Express. Disclosed is a computer program product that implements a method on a computer system and a PCI Express device/protocol for enabling high performance IO data transfers for multiple, different IO configurations, which include variable packet sizes and/or variable/different numbers of transactions on the IO link. PCI Express protocol is enhanced to support utilization of counters and dynamically variable queue sizes. In addition to the standard queue entries, several (or a selected number of) dynamically changeable queue entries are provided/reserved and a dynamic queue modification (DQM) logic is provided within the enhanced PCI Express protocol. The DQM logic monitors ongoing, current data transfer and manages when the size(s) of the queue entries are modified (increased or decreased) based on current data traffic transmitting on the PCI Express IO link. When data traffic tends towards a single stream of large data packets, queue entries are automatically combined and utilized to transfer the large data as quickly as possible. However, if the data traffic tends towards smaller data packets, the queue entries are broken up into many independent entries to handle the individual, smaller data packets. The enhanced PCI Express protocol provides an equilibrium point at which many large data packets are transferred efficiently, while imposing a limit on the number of each size of packets outstanding. The above as well as additional objectives, features, and advantages of the present invention will become apparent in the following detailed written description. The invention itself, as well as a preferred mode of use, further objects, and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein: Continue reading about Dynamically scalable queues for performance driven pci express memory traffic... Full patent description for Dynamically scalable queues for performance driven pci express memory traffic Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Dynamically scalable queues for performance driven pci express memory traffic patent application. Patent Applications in related categories: 20090287872 - Host computer with shared storage device - A host computer formed of a motherboard, a power supply unit with a power switch, a data storage device and an external interface is disclosed to have a transfer switch switcheable between a first switch position and a second switch position, the transfer switch having three contacts in the first ... ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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