Semiconductor device and method for manufacturing same

The present invention relates to a semiconductor device which comprises a plurality of source regions formed in a stripe shape on a semiconductor substrate, and a plurality of gate electrodes formed in a stripe shape on the semiconductor substrate between the stripe-shaped source regions, and to a method of manufacturing the same.

The power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and the IGBT (Insulated Gate Bipolar Transistor) as a discrete element used for switching power supply and the like are required to have high speed operating characteristics and low on-resistance properties. High speed operating characteristics are achieved by a planar structure having low capacitance characteristics.

For example, the MOSFET having a planar structure disclosed in Patent Document 1, as shown in FIG. 5, comprises a plurality of gate electrodes 2 formed in a stripe shape on an N type semiconductor board 1, P⁻ type base layers 3 and N⁺ type source layers 4 formed in a self-aligned manner by double diffusion with respect to the gate electrodes 2, an interlayer insulating film 5 to cover the gate electrode 2, and a source electrode (not shown) formed of metal film and formed on the interlayer insulating film 5. A plurality of P⁻ type base layers 3 and a plurality of N⁺ type source layers 4 are formed in a stripe shape along the gate electrodes 2. On the N⁺ type source layer 4, the interlayer insulating film 5 is formed with stripe shaped contact holes 7 along the entire length in a longitudinal direction of the source layer 4. The source electrode enters through the contact hole 7 to form an ohmic junction with the source layer 4.

With such structure, after the common connection of the plurality of gate electrodes 2 is made and the gate electrodes 2 are applied with a voltage larger than the predetermined threshold voltage, a surface portion of the base layer 3 is formed with an inversion layer and electricity is conducted between the semiconductor substrate 1 (drain) and the source layer 4, thus achieving transistor operation.

With the structure mentioned above, however, the contacts hole 7 must depend their formation upon lithography, and so that the spacing between the adjacent gate electrodes 2 are subjected to the limitation due to the minimum size of the contact hole 7 and the mask alignment tolerance (margin) for the formation of the gate electrode 2 and the contact hole 7.

On this account, the structure limits the refining of the pattern by reducing the spacing between the gate electrodes 2 and hampers an attempt for the improvement in the gate width (the total extension of the portion opposing to the source layer 4 in the gate electrode 2) per unit area, which limits the reduction in the on-resistance.

On the other hand, when the width of the gate electrode 2 is reduced, the number of the gate electrodes 2 per unit area can be increased, and the gate width can also be increased. However, it may cause a problem that the resistance of the gate electrode 2 (gate-resistance) is increased and the high speed operation is hampered.

It is, therefore, an object of the present invention to provide a semiconductor device that is capable of reducing the on-resistance without sacrificing the operation speed, and a method of manufacturing the same.

The semiconductor device according to the present invention comprises a semiconductor substrate; a plurality of source regions formed in a stripe shape on the semiconductor substrate; a plurality of gate electrodes formed in a stripe shape between the plurality of stripe shaped source regions on the semiconductor substrate; an insulating film for covering the source regions and the gate electrodes, the insulating film including a contact hole for partly exposing the source region in a part of a predetermined region with respect to a longitudinal direction of the source regions; and a source electrode formed on the insulating film and electrically connected to the source region via the contact hole.

According to this structure, the contact hole for connecting the source region and the source electrode is not formed over the entire length of the stripe shaped source region, but formed to only partly expose the source region in a part of a predetermined region with respect to a longitudinal direction of the source region. Therefore, the region other than the vicinity of the contact hole is able to reduce the spacing between the gate electrodes without being subjected to the limitation due to the minimum size of the contact hole and the mask alignment tolerance for the formation of the contact hole, and the width of the gate electrode need not be narrowed. Thus, the pattern can be refined and the gate width per unit area can be increased without leading to the increase in the gate-resistance, thereby reducing the on-resistance without sacrificing the operation speed.

The source region is formed in a stripe shape on the semiconductor substrate and each of the components are electrically connected with each other. Therefore, when the components are arranged to be partly contacted with the source electrode, the entire thereof is electrically connected to the source electrode.

It is preferable that the source region is processed to have a low resistance by applying silicide or the like on the surface thereof as appropriate. This can further reduce the on-resistance.

It is further preferable that the contact holes are disposed at a longitudinal end of the source region. With this structure, the contact hole contacts with the source electrode at the end portion of the source region thereby to effectively utilize the central region of the semiconductor substrate.

It is furthermore preferable that the contact holes are disposed only at a longitudinal end of the source region, so that the stripe shaped gate electrode can have a narrower spacing with the adjacent gate electrode and each of the adjacent gate electrodes can have a greater width therebetween along a longer region.

As an alternative structure, the contact hole may be disposed only at a predetermined position (the central portion, for example) in the middle of a longitudinal direction of the source region.

It is preferable that a plurality of contact holes are disposed in spaced relation in the longitudinal direction of the source region. With this structure, the electrical connection between the source region and the source electrode can be further ensured. In addition, in a region between the contact holes, sufficient gate electrode width can be maintained and at the same time the spacing between the adjacent gate electrodes can be made narrower, thereby increasing the gate width without sacrificing the gate-resistance.

It is preferable that the gate electrode includes a narrow width portion disposed at the side of the contact hole and a wide width portion having a wider width than the narrow portion. With this structure, on the one hand, the gate electrode has a narrower width at the side of the contact hole so as to ensure a distance between the gates in consideration of the minimum size of the contact hole and the mask alignment tolerance for the formation of the contact hole, and on the other hand, the gate electrode has a greater width at the other portion (preferably, the entire region except the side of the contact hole) so as to ensure a width that can achieve sufficient on-resistance. As a result, the electrical connection between the source region and the source electrode can be ensured. In addition, the spacing between the adjacent gate electrodes can be reduced so as to achieve a finer structure without sacrificing the gate-resistance, thereby increasing the gate width.