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05/07/09 - USPTO Class 718 |  39 views | #20090119671 | Prev - Next | About this Page  718 rss/xml feed  monitor keywords

Registers for data transfers

USPTO Application #: 20090119671
Title: Registers for data transfers
Abstract: A system and method for employing registers for data transfer in multiple hardware contexts and programming engines to facilitate high performance data processing. The system and method includes a processor that includes programming engines with registers for transferring data from one of the registers residing in an executing programming engine to a subsequent one of the registers residing in an adjacent programming engine. (end of abstract)



Agent: Fish & Richardson, PC - Minneapolis, MN, US
Inventors: GILBERT WOLRICH, Mark B. Rosenbluth, Debra Bernstein, Matthew Adiletta, Hugh M. Wilkinson, III
USPTO Applicaton #: 20090119671 - Class: 718103 (USPTO)

Registers for data transfers description/claims


The Patent Description & Claims data below is from USPTO Patent Application 20090119671, Registers for data transfers.

Brief Patent Description - Full Patent Description - Patent Application Claims
  monitor keywords CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation application and claims priority to U.S. application Ser. No. 10/116,670, filed on Apr. 3, 2002 (issuing as U.S. Pat. No. 7,437,724), the content of which is incorporated herein in its entirety.

BACKGROUND

Parallel processing is an efficient form of information processing of concurrent events in a computing process. Parallel processing demands concurrent execution of many programs, in contrast to sequential processing. In the context of parallel processing, parallelism involves doing more than one thing at the same time. Unlike a serial paradigm where all tasks are performed sequentially at a single station or a pipelined machine where tasks are performed at specialized stations, with parallel processing, many stations are provided, each capable of performing and carrying out various tasks and functions simultaneously. A number of stations work simultaneously and independently on the same or common elements of a computing task. Accordingly, parallel processing solves various types of computing tasks and certain problems are suitable for solution by applying several instruction processing units and several data streams.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a processing system.

FIG. 2 is a detailed block diagram of the processing system of FIG. 1 where one of the embodiments of the invention may be advantageously practiced.

FIG. 3 is a block diagram of a functional pipeline unit of the processing system of FIG. 1.

FIG. 4 is a block diagram illustrating details of the processing system of FIG. 1 where one of the embodiments of the invention may be advantageously practiced.

FIG. 5 is a simplified block diagram of a context pipeline process.

FIG. 6 is a flowchart illustrating the process of a context pipeline where one of the embodiments of the invention may be advantageously practiced.

FIG. 7 is a flowchart illustrating the process of determining the address of the Next Neighbor registers.

DESCRIPTION Architecture

Referring to FIG. 1, a computer processing system 10 includes a parallel, hardware-based multithreaded network processor 12. The hardware-based multithreaded processor 12 is coupled to a memory system or memory resource 14. Memory system 14 includes dynamic random access memory (DPAM) 14a and static random access memory 14b (SRAM) . The processing system 10 is especially useful for tasks that can be broken into parallel subtasks or functions. Specifically, the hardware-based multithreaded processor 12 is useful for tasks that are bandwidth oriented rather than latency oriented. The hardware-based multithreaded processor 12 has multiple functional microengines or programming engines 16a-16h (collectively, programming engines 16) each with multiple hardware controlled threads that are simultaneously active and independently work on a specific task.



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Patent Applications in related categories:

20090293061 - Structural power reduction in multithreaded processor - A circuit arrangement and method utilize a plurality of execution units having different power and performance characteristics and capabilities within a multithreaded processor core, and selectively route instructions having different performance requirements to different execution units based upon those performance requirements. As such, instructions that have high performance requirements, such ...


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