Vertically aligned mode liquid crystal display

This application is Divisional Application of U.S. patent application Ser. No. 10/488,048 filed Feb. 7,2005, by Sahng Ik JUN and Woon-Yong PARK entitled “VERTICALLY ALIGNED MODE LIQUID CRYSTAL DISPLAY,” incorporated herein by reference, which claims priority of PCT Patent Application No. PCT/KR02/01187 filed Jun. 21, 2002 and Korean Patent Application No. 2002-25545 Filed May 9, 2002.

(a) Field of the Invention

The present invention relates to a vertically aligned mode liquid crystal display, and, in particular, to a vertically aligned mode liquid crystal display including an electrode with cutouts for securing wide viewing angle.

(b) Description of Related Art

A typical liquid crystal display (“LCD”) includes an upper panel with a reference electrode and color filters, a lower panel with thin film transistors (“TFTs”) and pixel electrodes and a liquid crystal layer with dielectric anisotropy interposed therebetween, and displays desired images by applying different voltages to the reference electrode and the pixel electrodes to generate electric field in the liquid crystal layer, which changes the orientations of liquid crystal molecules to control the light transmittance.

Among these LCDs, a vertically aligned mode LCD (referred to as a “VALCD hereinafter), which aligns the major axes of the liquid crystal molecules vertical to upper and lower panels in absence of electric field, is promising because of its high contrast ratio and wide viewing angle.

To implement wide viewing angle in the VALCD, a cutout pattern or protuberances are provided on the electrode. Both generate fringe field to regularly distribute tilt directions of the liquid crystal molecules into four directions, thereby giving wide viewing angle.

Meanwhile, a plurality of wires such as gate lines transmitting scanning signals and data lines transmitting image signals are provided on a panel with the TFTs (referred to as a “TFT array panel” hereinafter) for an LCD. These signal wires have their own resistances and are coupled with peripheral signal wires or the reference electrode of upper panel to generate coupling capacitances. The loads due to such a resistances and capacitances of respective wires generate the distortion of the signals transmitted via the signal wires such as RC delay. In particular, the capacitive coupling between the data lines and the reference electrode drives the liquid crystal molecules disposed therebetween to cause light leakage near the data line, thereby deteriorating the image quality, and the light leakage, in turn, forces to enlarge the black matrix to reduce the aperture ratio.

An object of the present invention is to improve image quality by reducing the load of a data wire.

Another object of the present invention is to reduce the light leakage near a data line by decreasing coupling capacitance between the data line and a reference electrode.

To accomplish these and other objects, the present invention arranges cutouts located opposite each other with respect to a data line have inversion symmetry.

In detail, a thin film transistor array panel for liquid crystal display is provided, which includes: an insulated substrate; a gate line formed on the insulating substrate; a gate insulating layer formed on the gate lines; a data line formed on the gate insulating layer; a passivation layer formed on the data line; and a plurality of pixel electrodes formed on the passivation layer and having a plurality of cutouts, wherein the cutouts of two adjacent pixel electrodes opposite each other with respect to the data line have an inversion symmetry.

The cutouts of each pixel electrode preferably includes a transverse cutout extending substantially in a transverse direction to partition the pixel electrode into upper and lower halves and two oblique cutouts extending in oblique directions and located in the upper and the lower halves of the pixel electrode, and the oblique cutouts are substantially perpendicular to each other. In addition, the TFT array panel may further include a plurality of storage electrode wires including a storage electrode line parallel to gate line and a storage electrode connected to the storage electrode line, and may further include a storage bridge connecting two adjacent storage electrode wires opposite each other with respect to the gate line.

A liquid crystal display is provided, which includes: a first insulating substrate; a plurality of first wires formed on the first insulating substrate; a plurality of second wires intersecting and insulated from the first wire; a plurality of pixel electrodes located on respective pixel areas defined by the first wires and the second wires; a plurality of thin film transistors, each having a gate electrode, a source electrode and a drain electrode respectively connected to one of first wires, one of the second wires and one of the pixel electrodes; a second insulating substrate opposite the first insulating substrate; a reference electrode formed on the second insulating substrate; a plurality of first domain partitioning member formed on one of the first insulating substrate and the second insulating substrate; and a plurality of second domain partitioning member formed on one of the first insulating substrate or the second insulating substrate, wherein the first and the second domain partitioning members of two adjacent pixel electrodes opposite each other with respect to one of the data lines have an inversion symmetry.

The first domain partitioning members of the pixel electrodes preferably includes a plurality of cutouts, the plurality of cutouts of one of the pixel electrodes include a transverse cutout extending substantially in a transverse direction to partition the pixel electrode into upper and lower halves and two oblique cutouts extending in oblique directions and located in the upper and the lower halves of the pixel electrode, and the oblique cutouts are substantially perpendicular to each other. It is preferable that oblique cutouts are interposed between the second domain partitioning members of the reference electrode, and each second domain partitioning member includes an oblique portion parallel to the oblique cutouts and an overlapping portion overlapping edges of the pixel electrodes. The first domain partitioning members of each pixel electrode preferably include a central cutout extending substantially along a transverse center line of the pixel electrode and forking into upper and lower branches diverging obliquely and two oblique cutouts extending in oblique directions and located respectively in a lower half and an upper half of the pixel electrode, and one of the second domain partitioning members of the reference electrode is interposed between the oblique cutouts of the first domain partitioning members and includes an oblique portion parallel to the oblique cutouts and an overlapping portion overlapping edges of at least one of the pixel electrodes and one of the data lines. The overlapping portion preferably overlaps the one of the data lines and adjacent two of the pixel electrodes opposite each other with respect to one of the data lines.

A method of manufacturing such a thin film transistor panel includes: forming a gate wire including a plurality of gate lines, a plurality of gate electrodes connected to the gate lines and a plurality of gate pads connected to the gate lines on an insulating substrate; forming a gate insulating layer; forming a semiconductor layer; forming a data wire including a plurality of data line intersecting the gate lines, a plurality of data pads connected to the data lines, a plurality of source electrodes adjacent to the gate electrodes and a plurality of drain electrodes disposed opposite the source electrodes by depositing and patterning a conductive material; forming a passivation layer; forming a plurality of contact holes exposing the gate pads, the data pads and the drain electrodes by patterning the passivation layer together with the gate insulating layer; and forming a plurality of auxiliary gate pads, a plurality of auxiliary data pads and a plurality of pixel electrodes respectively connected to the gate pads, the data pads and the drain electrodes via the contact holes by depositing and patterning a transparent conductive layer, wherein the formation of a plurality of pixel electrodes makes adjacent two of the pixel electrodes opposite each other with respect to one of data lines to have a substantial inversion symmetry.

It is preferable that the data wire and the semiconductor layer are formed together by one photolithography using a photoresist pattern having a first portion, a second portion thinner than the first portion, and a third portion thinner than second portion. The second portion is preferably located between one of the source electrodes and one of the drain electrodes and the first portion is located on the data wire in the one photolithography.