Synchronous address and data multiplexed mode for sram

1. Field of the Invention

The present invention relates to a synchronous memory system having a mode in which address and data signals can be multiplexed on the same set of signal lines.

2. Related Art

In some applications, such as cellular phones, there is a limited space for a printed circuit board (PCB). If an application uses a static random access memory (SRAM) chip that requires a 16-bit data bus and a 14-bit address bus, the associated PCB will require at least 30 corresponding routing wires to enable the SRAM chip to communicate with other chips.

It would therefore be desirable to share the address bus with the data bus, thereby minimizing the number of routing wires required on the PCB. An operating mode in which address and data signals are multiplexed onto the same set of bus lines is hereinafter referred to as a address/data (A/D) muxed mode.

Intel® provides a flash memory that shares an address bus with a data bus. This flash memory is described in more detail in the Datasheet for the Intel® StrataFlash® Cellular Memory (M18) (Order Number 309823). However, this Intel® flash memory can only perform asynchronous write operations, which require the use of extra control signals (i.e., extra PCB routing wires). Moreover, while the Intel® flash memory is capable of performing synchronous read operations, an acknowledge signal is required to indicate that the synchronous read data is ready. The acknowledge signal undesirably requires an additional PCB routing wire.

It would therefore be desirable to have a memory system that can perform fully synchronous write and read operations, while multiplexing address and data signals on the same set of bus lines, and minimizing the required number of PCB routing wires. It would be desirable for the timing specifications of this memory system to be well defined with respect to a system clock signal, such that an acknowledge signal is not required to perform synchronous read operations. It would further be desirable for write address and write data signals to be processed in response to well defined clock edges, and for read data signals to be provided in response to well defined clock edges. It would further be desirable for the memory system to be capable of performing single address write/read operations, burst write/read operations, and repeat write/read operations in the A/D muxed mode.

Accordingly, the present invention provides a synchronous memory system that includes a bus configuration circuit that can be controlled to operate from dedicated address and data buses (non-multiplexed mode) or from a multiplexed A/D bus (multiplexed mode). If the synchronous memory system supports multiple ports, then each port can be independently configured to operate in either the multiplexed mode or the non-multiplexed mode.

When configured in the multiplexed mode, read and write accesses are qualified by a plurality of memory access control signals, including an address strobe signal, an address counter enable signal and an address repeat signal. To implement a read access, at least one of the memory access control signals is activated and a read/write control signal is controlled to identify a read operation (i.e., placed in a ‘read’ state). The read access is initiated upon detecting these conditions at a rising edge of the system clock signal. The end of the read access is identified by de-activating all of the memory access control signals and maintaining the read/write control signal in the read state. Using these rules, N read accesses can be implemented in N+2 cycles of the system clock signal.

To implement a write access, at least one of the memory access control signals is activated and a read/write control signal is controlled to identify a write operation (i.e., placed in a ‘write state). The write access is initiated upon detecting these conditions at a rising edge of the system clock signal. The end of the write access is identified by de-activating all of the memory access control signals and maintaining the read/write control signal in the write state. Using these rules, N write accesses can be implemented in N+1 cycles of the system clock signal.

Signal timing on the multiplexed address/data bus is well defined in the multiplexed mode, such that no output enable signal is required in this mode.

The present invention will be more fully understood in view of the following description and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a waveform diagram illustrating the timing of a single write cycle in accordance with one embodiment of the present invention.

FIG. 1B is a waveform diagram illustrating the timing of a burst write cycle, during which three data values are written to three consecutive addresses of a memory core, in accordance with one embodiment of the present invention.

FIG. 2A is a waveform diagram illustrating the timing of a single read cycle in accordance with one embodiment of the present invention.

FIG. 2B is a waveform diagram illustrating the timing of a burst read cycle, during which three data values are read from three consecutive addresses of a memory core, in accordance with one embodiment of the present invention.

FIG. 3 is a block diagram of a memory system that implements an A/D muxed mode (as well as a non-A/D muxed mode) in accordance with one embodiment of the present invention.

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