The present application claims priority to German Application No. 10 2007 046 556 filed Sep. 28, 2007, which is incorporated by reference herein in its entirety.
FIELD OF THE INVENTION
- Top of Page
The invention relates to a semiconductor component comprising at least one cell formed in a semiconductor substrate and comprising at least one metallization layer arranged above the semiconductor substrate and composed of copper or a copper alloy for the electrical connection of the cell.
- Top of Page
Semiconductor components, in particular for power applications, are often constructed in the form of cells which can be used to form a multiplicity of, in particular, semiconductor structures of identical type in a semiconductor component. This structure is used in particular for switches for controlling high currents, such as, for example, field-effect transistors, bipolar transistors, IGBTs or thyristors. In this case, an evolution of heat occurs in the semiconductor component on account of the current loading, which evolution of heat thermally loads the various parts of the semiconductor component and can lead to damage to the semiconductor component.
Furthermore, in power semiconductors a low electrical resistance is advantageous in order that the electrical losses in the semiconductor component and thus also the evolution of heat are kept small. This can be achieved by using conductor structures having a high cross section, although conductor structures having a high cross section lead to problems upon thermal loading on account of the thermal expansion.
- Top of Page
OF THE INVENTION
A semiconductor component has in a semiconductor substrate at least one cell comprising a first and a second main electrode zone and a control electrode zone lying in between. At least one metallization layer composed of copper or a copper alloy is arranged above the semiconductor substrate, and is connected to at least one bonding electrode and electrically coupled to at least one main electrode zone. The at least one bonding electrode comprises copper or a copper alloy. Copper is used hereinafter as synonymous with copper or copper alloy.
BRIEF DESCRIPTION OF THE FIGURES
FIG. 1 shows a cross section through a section of a semiconductor component in accordance with a first exemplary embodiment with a plurality of vertical field-effect transistors arranged in elongate cells, transversely with respect to the course of the cells,
FIG. 2 shows a plan view of the section of the semiconductor component according to FIG. 1,
FIG. 3 shows a cross section through part of a semiconductor component in accordance with a second exemplary embodiment with lateral field-effect transistors,
FIG. 4 shows a cross section through part of a semiconductor component in accordance with a third exemplary embodiment with a single metallization layer, and
FIG. 5 shows a plan view of a section of a semiconductor component in accordance with a fourth exemplary embodiment.
- Top of Page
The semiconductor component illustrated sectionally in part in FIG. 1 has a semiconductor substrate 1 composed of silicon, in which a total of eight transistors are formed which are elongate and extend perpendicular to the plane of the drawing. The transistors are field-effect transistors and each have a source zone S and a drain zone D, wherein the drain zones D of all the transistors form a single doped region and the source zones S of two adjacent transistors together form a doped region.
Situated between the source zones S and the drain zones D is in each case a channel region B, which is also called a body zone. The source zones S and the drain zones D form the main electrode regions through which the current controlled by the transistors flows. These main electrode regions S, D are connected to main electrode zones or merge into main electrode zones which are connected to further conductors outside the semiconductor substrate 1.
Above the channel regions B, outside the semiconductor substrate 1, gate electrodes G are provided in a manner isolated from the channel regions B by a thin insulating layer. The insulating layer between the channel regions B and the gate electrodes G is a thin silicon oxide layer.
Furthermore, the semiconductor substrate 1 is covered with a silicon oxide layer having openings in the region of the source islands S and of the drain connection region D, plated-through holes of a first metal layer M1 arranged above the semiconductor substrate 1 being arranged in said openings.
The drain zones D together form a drain connection region that runs laterally within the semiconductor substrate 1 and, at the sides of the cell array, extends upwards as far as that side of the semiconductor substrate 1 in which the source islands S are arranged. The main electrode zones for the source islands S and the drain islands D are thus situated on the same side of the semiconductor substrate 1.
The first metallization layer M1 comprises copper or a copper alloy and is produced in accordance with a dual damascene process, such that the plated-through holes at the underside of the first metallization layer M1 are formed integrally with the latter from the same material. A barrier layer (not illustrated) composed of titanium/tungsten-titanium is arranged between the copper material of the first metallization layer M1 and the semiconductor substrate. In addition, in a variant of this embodiment it is also possible to produce the plated-through holes below the first metallization layer M1 from tungsten and then, in a second work step, to form the first metallization layer M1 from copper thereabove in a single damascene process. The first metallization layer M1 is patterned into islands M1D, M1S, three of which are illustrated in FIG. 1. The two outer islands M1D are each connected to the drain main electrode zone D and the middle island M1S is connected to the four source main electrode zones S.
A second metallization layer M2 likewise composed of copper or of a copper alloy is arranged above the first metallization layer M1. The second metallization layer M2 is produced in accordance with the dual damascene process, such that plated-through holes formed integrally at the bottom on the second metallization layer and composed of the same material are formed through to the underlying first metallization layer M1.
The same applies to a further third metallization layer M3 formed above the second metallization layer M2. A power metallization layer PM is arranged above the third metallization layer M3, said power metallization layer being connected to third islands M3D of the third metallization layer M3.
A bonding electrode 2 composed of copper or a copper alloy is fixed at the top on the power metallization layer PM.
The islands of the individual metallization layers M1 to M3 which are in each case arranged one above another and connected to one another contact-connect the two main electrode zones D, S as far as towards the top to the power metallization layer PM.
FIG. 2 illustrates a plan view of that part of the semiconductor component which is illustrated sectionally in FIG. 1. The illustration of the gate electrodes G was dispensed with in this view for the sake of better clarity. The contours of the elongate main electrode zones D, S are illustrated in dotted fashion at the very bottom. In this case it can be discerned that a wide drain main electrode zone D is respectively arranged on the outer side and four narrower elongate source main electrode zones S are arranged in between. All the main electrode zones D, S are arranged parallel to one another and have at least substantially the same length.
First drain islands M1D of the first metallization layer M1 are in each case arranged on the two drain main electrode zones D, said first drain islands having substantially the same elongate, rectangular contour as the underlying drain main electrode zones D and being electrically connected to the latter downwards over the entire length of the main electrode zones D. An electrical connection over the entire length should generally be understood within this description as the provision of contact locations at least substantially over the entire length, wherein a single contact location extending in large-area fashion over the length or else a plurality of contact locations distributed over the length can be provided.
The source main electrode zones S are connected to a first source island M1S of the first metallization layer M1, which is electrically connected to the four source main electrode zones S over the entire length thereof. The first source island M1S of the first metallization layer M1 is accordingly significantly wider than the two first drain islands M1D.
Arranged above the first islands M1D, M1S are second islands M2D, M2S of the second metallization layer M2, which are illustrated by a dash-dotted line and are electrically connected to the respective underlying first island M1D, M1S over the entire length thereof. In this case, second drain islands M2D are arranged above the outer first drain islands M1D, said second drain islands having at least substantially the same contour as the first drain islands M1D. A second source island M2S is arranged above the middle first source island M1S. The second source island M2S has the form of a trapezium or of a rectangle that tapers in the longitudinal direction. The length of the second source island M2S corresponds at least substantially to the length of the first source island M1S. The width of the second source island M2S increases towards the bottom in the drawing. In principle, in the drawings the contours of islands lying one above another are depicted alongside one another for the sake of better clarity, even if the contours can lie one above another, such as in the present case for example the contours of the drain main electrode zones D, of the overlying first drain islands M1D and of the second drain islands M2D arranged thereabove.
The second drain islands M2D have at least substantially the same contour as the underlying first drain islands M1D.
Third islands M3D, M3S are respectively arranged above the second islands M2D, M2S. Two third drain islands M3D are respectively arranged above the two second drain islands M2D. The third drain islands M3D have a trapezium form or the form of a narrowing elongate rectangle which extends in the longitudinal direction of the second drain islands M2D. The width of the third drain islands M3D decreases in the direction in which the width of the second source island M2S increases. The third drain islands M3D are electrically connected to the respective underlying second drain islands M2D over the entire length thereof. Arranged above the second source island M2S is a third source island M3S, which has a trapezium form similar to that of the second source island M2S but is narrower overall. This has the effect that the third drain islands M3D have the same distance horizontally laterally inwards with respect to the third source region M3S as inwards obliquely downwards with respect to the second source island M2S, such that the required dielectric strength is achieved with good utilization of the space for current-carrying interconnects.