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Constant phase digital attenuator with on-chip matching circuitry

Constant phase digital attenuator with on-chip matching circuitry description/claims

Electronic devices often incorporate controllable attenuation devices and/or components for varying the amount of resistance applied to electronic signals such as radio frequency (RF) signals. Such attenuators are used in, among other things, automatic gain control circuits, position locating systems, telephone systems, television systems, and microwave circuit applications.

Some controllable attenuation devices such as monolithic microwave integrated circuit (MMIC) digital attenuators incorporate high frequency field effect transistors (FETs), such as gallium arsenide (GaAs) metal semiconductor FETs, arranged in a variety of network configurations (which may include other circuit elements, e.g., discrete resistor, among others). These devices operate by turning certain transistors on and off to adjust or select the desired attenuation.

Digital attenuators vary the strength of input signals in response to digital control signals. In a typical 1-bit digital attenuator, the amount of attenuation offered by the attenuator varies depending on whether the bit of the control signal has a value of “0” (logic low) or “1” (logic high). Typically, if a 2-bit or other multiple-bit digital attenuator is desired, a plurality of 1-bit digital attenuators are cascaded according to known techniques to produce the desired m-bit digital attenuator (where m≧2). For example, if a 3-bit digital attenuator is desired, three of the 1-bit digital attenuators are cascaded to produce the 3-bit digital attenuator.

Due to the cascading of bits, however, a reference insertion loss in conventional multi-bit digital attenuators tends to be high resulting in higher Voltage Standing Wave Ratio (VSWR), which represents the amount of reflected power. A high VSWR increases noise, which degrades system performance. Further, having multiple bits that are cascaded in the digital attenuator deteriorates the attenuation accuracy when multiple bits are switched on at the same time.

For certain applications, it is desirable to have a constant phase over attenuation states. Usually, for lower bits and at lower frequencies, phase shift may be less and manageable using techniques such as cascading lower bits. At higher frequencies, however, conventional digital attenuators may experience significant phase difference between the on and off states.

Accordingly, there exists the need for an improved digital attenuator to provide constant phase at higher frequencies.

FIG. 1 illustrates one embodiment of a constant phase digital attenuator circuit.

FIG. 2 illustrates one embodiment of a multi-stage constant phase digital attenuator.

FIG. 3 illustrates an on-chip layout of one embodiment of a multi-stage constant phase digital attenuator.

Various embodiments are directed to providing constant phase digital attenuation. In one embodiment, a digital attenuator circuit comprises an input node to receive an input signal to be attenuated, an output node to output an attenuated signal, a reference loss path between the input node and the output node, and an attenuation path between the input node and the output node. The reference loss path comprises switching elements and matching circuitry to improve Voltage Standing Wave Ratio (VSWR), and the attenuation path comprises switching elements and attenuating circuitry to attenuate the input signal when the digital attenuator circuit is switched from a reference loss state to an attenuation state. An effective phase length of the reference loss path and an effective phase length of the attenuation path may be equalized to provide a constant phase when the digital attenuator circuit is switched between states.

In one embodiment, a multi-stage digital attenuator includes a plurality of digital attenuator circuits with each digital attenuator circuit comprising a stage of the multi-stage digital attenuator circuit. The multi-stage digital attenuator includes a plurality of interstage inductance elements implemented as high impedance transmission lines to match the output of a previous stage and the input of a next stage. The plurality of digital attenuator circuits forming the multi-stage digital attenuator may be implemented on a single chip.

In one embodiment, a method includes providing a digital attenuator circuit on a chip. The digital attenuator circuit includes a reference loss path comprising switching elements and matching circuitry to improve VSWR and an attenuation path comprising switching elements and attenuating circuitry to attenuate an input signal when the digital attenuator circuit is switched from a reference loss state to an attenuation state. An effective phase length of the reference loss path and an effective phase length of the attenuation path may be equalized to provide a constant phase when the digital attenuator circuit is switched between states. A plurality of digital attenuator circuits may be provided on the chip to implement a multi-stage digital attenuator, and interstage inductance elements comprising high impedance transmission lines may be provided to couple digital attenuator circuits.

FIG. 1 illustrates one embodiment of a constant phase digital attenuator circuit 100. Digital attenuator circuit 100 comprises RF input node 102 and RF output node 104. While it can be appreciated that digital attenuator circuit 100 comprises a symmetrical structure, it will be assumed for purposes of illustration that the left node comprises RF input node 102 and right node comprises RF output node 104. The embodiments, however, are not limited in this regard.

• Provisional Patent
• Utility Patent

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