Site News  |   Monitor Keywords  |   Monitor Archive  |   Organizer  |   Account Info  |

Simultaneous multi-layer fill generation

Simultaneous multi-layer fill generation description/claims

This application claims priority under 35 US.C. §119 to U.S. Provisional Patent Application No. 60/930,596 entitled “Simultaneous Multi-Layer Fill Generation,” filed on May 16, 2007, naming Eugene Anikin et al. as inventor, and to U.S. Provisional Patent Application No. 61/039,100 entitled “Simultaneous Multi-Layer Fill Generation,” filed on Mar. 24, 2008, naming Eugene Anikin et al. as inventor, which applications are incorporated entirely herein by reference. This application also claims priority under 35 U.S.C. §120 to U.S. patent application Ser. No. 11/743,116, entitled “Optimization Of Pattern Density,” filed on May 1, 2007, naming Eugene Anikin as inventor, which in turn claims priority under 35 U.S.C. §119 to U.S. Provisional Patent Application No. 60/853,309 entitled “Optimization Of Pattern Density,” filed on May1, 2006, naming Eugene Anikin as inventor, and originally assigned U.S. patent application Ser. No. 11/415,878, which applications are incorporated entirely herein by reference as well.

The present invention relates to various techniques and tools to assist in the design of circuits, such as integrated circuits. Various aspects of the present invention are particularly applicable to optimizing the densities of structures in multiple layers of a circuit.

Electronic circuits, such as integrated microcircuits, are used in a variety of products, from automobiles to microwaves to personal computers. Designing and fabricating microcircuit devices typically involve many steps, known as a “design flow.” The particular steps of a design flow are highly dependent upon the type of microcircuit being designed, its complexity, the design team, and the microcircuit fabricator or foundry that will manufacture the microcircuit. Typically, software and hardware “tools” will verify a design at various stages of the design flow by running software simulators and/or hardware emulators, and errors in the design are corrected.

Several steps are common to most design flows. Initially, the specification for the new microcircuit is transformed into a logical design, sometimes referred to as a register transfer level (RTL) description of the circuit. With this logical design, the circuit is described in terms of both the exchange of signals between hardware registers and the logical operations that are performed on those signals. The logical design typically employs a Hardware Design Language (HDL), such as the Very high speed integrated circuit Hardware Design Language (VHDL). The logical of the circuit is then analyzed, to confirm that the logic incorporated into the design will accurately perform the functions desired for the circuit. This analysis is sometimes referred to as “functional verification.”

After the accuracy of the logical design is confirmed, it is converted into a device design by synthesis software. The device design, which is typically in the form of a schematic or netlist, describes the specific electronic devices (such as transistors, resistors, and capacitors) that will be used in the circuit, along with their interconnections. This logical generally corresponds to the level of representation displayed in conventional circuit diagrams. Preliminary timing estimates for portions of the circuit may be made at this stage, using an assumed characteristic speed for each device. In addition, the relationships between the electronic devices are analyzed, to confirm that the circuit described by the device design will correctly perform the functions desired for the circuit. This analysis is sometimes referred to as “formal verification.”

Once the relationships between circuit devices have been established, the design is again transformed, this time into a physical design that describes specific geometric elements. This type of design often is referred to as a “layout” design. The geometric elements define the shapes that will be created in various materials to actually manufacture the circuit device components (e.g., contacts, gates, etc.) making up the circuit. While the geometric elements are typically polygons (and are often colloquially referred to as “polygons”), other shapes, such as circular and elliptical shapes, also may be employed. These geometric elements may be custom designed, selected from a library of previously-created designs, or some combination of both. Geometric elements also are added to form the connection lines that will interconnect these circuit devices. Layout tools (often referred to as “place and route” tools), such as Mentor Graphics' IC Station or Cadence's Virtuoso, are commonly used for both of these tasks.

With a layout design, each physical layer of the microcircuit will have a corresponding layer representation, and the geometric elements described in a layer representation will define the relative locations of the circuit device components that will make up a circuit device. Thus, the geometric elements in the representation of an implant layer will define the regions where doping will occur, while the geometric elements in the representation of a metal layer will define the locations in a metal layer where conductive wires used will be formed to connect the circuit devices. Typically, a designer will perform a number of analyses on the layout design. For example, the layout design may be analyzed to confirm that it accurately represents the circuit devices and their relationships described in the device design. The layout design also may be analyzed to confirm that it complies with various design requirements, such as minimum spacings between geometric elements. Still further, it may be modified to include the use of redundant or other compensatory geometric elements intended to counteract limitations in the manufacturing process, etc. After the layout design has been finalized, it then is converted into a format that can be employed by a mask or reticle writing tool to create a mask or reticle for use in a photolithographic manufacturing process.

Modern integrated circuits typically will be formed of multiple layers of material, such as metal, diffusion material, and polysilicon. During the manufacturing process, layers of material are formed sequentially on top of one another. After each layer is created, portions of the layer are removed to form various structures corresponding to the shape of the geometric elements in layout design. Together, the structures of material form the functional circuit devices, as noted. Before a new layer is formed over the structures in an existing layer, however, the existing layer must be polished to ensure planarity. Polishing using any of various types of polishing processes sometimes is referred to generically as “planarization.”

One problem with conventional planarization methods is that different materials will have different densities, so softer materials will be polished more deeply than harder materials. As a result, a layer's surface may become uneven, causing the next layer to be more uneven. In some situations, the uppermost layers of material may have a very irregular surface topography. Such irregular surface topographies may cause a variety of flaws in the circuit structures, such as holes, loss of contact, and other manufacturing defects.

To improve the planarity of a layer of material, the integrated circuit designer (or manufacturer) often will analyze a circuit layout design for empty regions in the layer. That is, the designer or manufacturer will review the pattern density of the geometric elements in the design for a layer, to identify regions that are empty of geometric elements. The designer or manufacturer will then modify the circuit layout design to fill these empty regions with data representing “dummy” or “fill” geometric elements. That is, the designer or manufacturer will increase the density of geometric elements in the circuit layout design for the layer. When the circuit is manufactured, “fill” structures will be formed by the fill geometric elements alongside “functional” structures (i.e., the structures the form the components of functional circuit devices), so that the overall surface of the layer is relatively flat. This type of corrective technique will often be implemented using a software application for identifying and manipulating the geometric elements defined in a circuit layout design, such as the CALIBRE® verification and manufacturability software tools available from Mentor Graphics® Corporation of Wilsonville, Oreg.

While this corrective technique usually improves the planarity of layers in an integrated circuit, it has some drawbacks. First, a user must typically divide a layer design into multiple smaller area or “windows,” and then manually identify and fill the empty regions on a window-by-window basis. This process can be very time consuming and tedious. Moreover, because the fill geometric elements are added to only a single layer at a time, this tedious process must be repeated for each layer in the design needing fill geometric elements.

Moreover, adding fill geometric elements may increase the capacitance of the layer. If the designer or manufacturer inadvertently fills too much of the empty regions in a design with fill geometric elements, or places fill geometric elements too close to functional geometric elements in the design, the resulting increased capacitance may cause the circuit devices around the fill structures to exceed their minimum timing requirements. Adding fill geometric elements that are too close to functional geometric elements also may increase the occurrence of bridging faults between the fill structures and the functional structures when the circuit is manufactured. Still further, each additional fill geometric element may increase the time and complexity of optical proximity correction processing or resolution enhancement technology processing of the circuit layout design prior to manufacture.

Advantageously, various examples of the invention provide techniques for optimizing the pattern density in the circuit layout design of a circuit layer. According to various implementations of the invention, a layer in circuit design is analyzed to define empty regions that can be filled with fill polygons (referred to hereafter as “fill” regions). With some examples of the invention, a designer or manufacturer may specify constraints for defining the fill regions, so that fill polygons cannot inadvertently be placed too closely to functional polygons. Next, a pattern of fill polygons is generated. For some implementations of the invention, a designer or manufacturer may create a repeating pattern of a fill polygon of any desired size and shape, or even a combination of multiple fill polygons of any desired sizes and shapes. Thus, an initial polygon fill pattern may contain relatively large fill polygons, to minimize the number of fill polygons required to fill the fill regions. Subsequent iterations of the fill process may then use fill polygons of progressively smaller sizes, in order to maximize the area of the fill regions filled with fill polygons.

After the fill polygons have been defined, the layout design for the layer is divided into separate areas or “windows,” and a target density for each window is determined. More particularly, each window is analyzed with respect to its adjacent windows, to determine a target density for the window that will satisfy specified density constraint values, such as a minimum density constraint, a maximum density constraint, or a maximum density gradient constraint. Various examples of the invention will attempt to determine the smallest target density for the window that will comply with each of the specified density value constraints. Thus, some examples of the invention may attempt to determine a target density that will be both greater than a specified minimum density constraint, and ensure that the density gradient between the window and its adjacent windows is less than a specified maximum density gradient. Once this target density for the window has been determined, the fill polygons required to most closely approach this target density are generated and added to the circuit layout design. With some implementations of the invention, for example, fill polygons are selected individually from the fill polygon pattern based upon a difference between the determined target window density and the current window density, as well as the area occupied by each fill polygon. The selected fill polygons are then added to the fill regions in the circuit layout design. With some examples of the invention, this process may be repeated with progressively different (e.g., smaller) fill polygons, until each window meets or exceeds both the specified minimum density and complies with the specified maximum density gradient.

Various implementations of the invention allow a user to simultaneously optimize the density of multiple layers of a circuit by designing fill structures that exist in one or more of these layers. That is, embodiments of the invention may allow a user to add geometric fill elements to multiple layers of a circuit design simultaneously. For example, a user may designate a target structure density value for a three-dimensional window in the design where the window includes a portion of two or more layers in the circuit design. The target structure density value may be a minimum density value for one or more portions within the window, or a cumulative density value for the entirety of the window. Representations of a multilayer fill structure section will then be added to the circuit design until the target density is met.

• Provisional Patent
• Utility Patent

• What Is a Patent?
• What Is a Trademark or Servicemark?
• What Is a Copyright?
• Patent Laws