Follow us on Twitter
twitter icon@FreshPatents

Browse patents:
Next
Prev

Depletion mode field effect transistor for esd protection




Title: Depletion mode field effect transistor for esd protection.
Abstract: The object of this invention is to present a field effect transistor by which the drain capacitance per unit gate width can be reduced. The gate electrode 21 (G) having a plurality of sides is formed in first-conductivity first semiconductor region 14, drain region 18D (D) is formed inside the gate electrode, and source regions 18S (S) are formed in the respective regions outside the plurality of sides in widths that do not reduce the corresponding channel widths of the drain region. The gate electrode is formed along all the plurality of sides of the drain region in order to form a transistor. ...


- Dallas, TX, US
USPTO Applicaton #: #20090072314
Inventors: Yohichi Okumura, Josef Muenz


The Patent Description & Claims data below is from USPTO Patent Application 20090072314, Depletion mode field effect transistor for esd protection.

Advertise on FreshPatents.com - Rates & Info


You can also Monitor Keywords and Search for tracking patents relating to this Depletion mode field effect transistor for esd protection patent application.

###

Keyword Monitor How KEYWORD MONITOR works... a FREE service from FreshPatents
1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored.
3. Each week you receive an email with patent applications related to your keywords.  
Start now! - Receive info on patent apps like Depletion mode field effect transistor for esd protection or other areas of interest.
###


Previous Patent Application:
Metal high-k (mhk) dual gate stress engineering using hybrid orientation (hot) cmos
Next Patent Application:
Semiconductor manufacturing process charge protection circuits
Industry Class:
Active solid-state devices (e.g., transistors, solid-state diodes)
Thank you for viewing the Depletion mode field effect transistor for esd protection patent info.
- - -

Results in 0.0869 seconds


Other interesting Freshpatents.com categories:
Nokia , SAP , Intel , NIKE ,

###

Data source: patent applications published in the public domain by the United States Patent and Trademark Office (USPTO). Information published here is for research/educational purposes only. FreshPatents is not affiliated with the USPTO, assignee companies, inventors, law firms or other assignees. Patent applications, documents and images may contain trademarks of the respective companies/authors. FreshPatents is not responsible for the accuracy, validity or otherwise contents of these public document patent application filings. When possible a complete PDF is provided, however, in some cases the presented document/images is an abstract or sampling of the full patent application for display purposes. FreshPatents.com Terms/Support
-g2-0.0617

66.232.115.224
Browse patents:
Next
Prev

stats Patent Info
Application #
US 20090072314 A1
Publish Date
03/19/2009
Document #
File Date
12/31/1969
USPTO Class
Other USPTO Classes
International Class
/
Drawings
0




Follow us on Twitter
twitter icon@FreshPatents

Texas Instruments Incorporated



Active Solid-state Devices (e.g., Transistors, Solid-state Diodes)   Field Effect Device   Having Insulated Electrode (e.g., Mosfet, Mos Diode)   With Overvoltage Protective Means  

Browse patents:
Next
Prev
20090319|20090072314|depletion mode field effect transistor for esd protection|The object of this invention is to present a field effect transistor by which the drain capacitance per unit gate width can be reduced. The gate electrode 21 (G) having a plurality of sides is formed in first-conductivity first semiconductor region 14, drain region 18D (D) is formed inside the |Texas-Instruments-Incorporated
';