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Identifying and improving robust designs using statistical timing anaysis

Identifying and improving robust designs using statistical timing anaysis description/claims

1. Field of the Invention

The invention relates to integrated circuit (IC) designs and in particular to identifying robust designs and improving such design using statistical timing analysis.

2. Related Art

FIG. 1 illustrates a simplified representation of an exemplary digital IC design flow. At a high level, the process starts with the product idea (step 100) and is realized in an EDA software design process (step 110). When the design is finalized, it can be taped-out (event 140). After tape out, the fabrication process (step 150) and packaging and assembly processes (step 160) occur resulting, ultimately, in finished chips (result 170).

The EDA software design process (step 110) is actually composed of a number of steps 112-130, shown in linear fashion for simplicity. In an actual ASIC design process, the particular design might have to go back through steps until certain tests are passed. Similarly, in any actual design process, these steps may occur in different orders and combinations. This description is therefore provided by way of context and general explanation rather than as a specific, or recommended, design flow for a particular ASIC.

A brief description of the components steps of the EDA software design process (step 110) will now be provided:

System design (step 112): The designers describe the functionality that they want to implement, they can perform what-if planning to refine functionality, check costs, etc. Hardware-software architecture partitioning can occur at this stage. Exemplary EDA software products from Synopsys, Inc. that can be used at this step include Model Architect, Saber, System Studio, and DesignWare® products.

Logic design and functional verification (step 114): At this stage, the VHDL or Verilog code for modules in the system is written and the design is checked for functional accuracy. More specifically, the design is checked to ensure that it produces the correct outputs. Exemplary EDA software products from Synopsys, Inc. that can be used at this step include VCS, VERA, DesignWare®, Magellan, Formality, ESP and LEDA products.

Synthesis and design for test (step 116): Here, the VHDL/Verilog is translated to a netlist. The netlist can be optimized for the target technology. Additionally, the design and implementation of tests to permit checking of the finished chip occurs. Exemplary EDA software products from Synopsys, Inc. that can be used at this step include Design Compiler®, Physical Compiler, Test Compiler, Power Compiler, FPGA Compiler, Tetramax, and DesignWare® products.

Netlist verification (step 118): At this step, the netlist is checked for compliance with timing constraints and for correspondence with the VHDL/Verilog source code. Exemplary EDA software products from Synopsys, Inc. that can be used at this step include Formality, PrimeTime, and VCS products.

Design planning (step 120): Here, an overall floorplan for the chip is constructed and analyzed for timing and top-level routing. Exemplary EDA software products from Synopsys, Inc. that can be used at this step include Astro and IC Compiler products.

Physical implementation (step 122): The placement (positioning of circuit elements) and routing (connection of the same) occurs at this step. Exemplary EDA software products from Synopsys, Inc. that can be used at this step include the Astro and IC Compiler products.

Analysis and extraction (step 124): At this step, the circuit function is verified at the physical and electrical levels. Exemplary EDA software products from Synopsys, Inc. that can be used at this step include AstroRail, PrimeRail, Primetime, and Star RC/XT products.

Physical verification (step 126): At this step various checking functions are performed to ensure correctness for: manufacturing, electrical issues, lithographic issues, and circuitry. Exemplary EDA software products from Synopsys, Inc. that can be used at this step include the Hercules product.

Resolution enhancement (step 128): This step involves geometric manipulations of the layout to improve manufacturability of the design. Exemplary EDA software products from Synopsys, Inc. that can be used at this step include Proteus, ProteusAF, and PSMGen products.

Mask data preparation (step 130): This step provides the “tape-out” data for production of masks for lithographic use to produce finished chips. Exemplary EDA software products from Synopsys, Inc. that can be used at this step include the CATS(R) family of products.

Netlist verification (step 118) can provide the expected timing of a digital circuit without simulation. This netlist verification technique, called static timing analysis (STA), provides a detailed analysis of the timing behavior of the circuit independent of the combinations of input values.

In STA terminology, a timing constraint is a budget of time that is available for circuit signals to propagate and be satisfactorily read at an output or captured by a memory element. The timing constraints are captured by user-specified information such as the clocking scheme, output loads, etc. A “critical path” is defined as the path between an input pin or an output of a memory element and an output pin or an input of a memory element which violates a timing constraint. The pin at which the timing check is performed is called an endpoint. Timing constraints can be categorized into two forms. A set-up constraint is one that requires the signal to be stable no later than the budget. A hold constraint is one that requires the signal to change no earlier than the budget. For sake of exposition and without loss of generality, only the first form is referred to herein. The arrival time of a pin is defined as time that the signal at the pin stabilizes. In static timing, the arrival can be computed using the “add” and “maximum” operations. The required time of a pin is the time at which the signal must stabilize to meet a timing constraint. In static timing, the required time can be computed using the “subtract” and “minimum” operations. The “slack” of a pin can be defined as the difference between the required time and the arrival time. Thus, a positive slack means that the overall delay of the circuit is acceptable (and, if desirable, arrival time at that pin can even be increased), whereas a negative slack means that the path is too slow and therefore must be sped up to avoid adversely affecting the overall delay of the circuit.

Over the last few years, variations in delay have concerned many in the industry. Delay variations can arise from changes in the operating conditions such as voltage and temperature as well as process variations that arise during manufacturing. However, in the context of a design flow, variations in delay can also stem from the optimization in down-stream tools, the refinement of models used in computation as the design evolves, and any changes to the design (i.e. specification changes).

Unfortunately, characterizing each cause of the change and then attempting to define the “robustness” of a circuit with respect to that change would require significant resource allocation. Therefore, there arises a need for a method and an apparatus to construct change-tolerant designs in a cost-effective manner.

A relatively new extension to static timing analysis known as statistical timing analysis has been introduced. This technology has been designed to model variations in circuit delays caused by process variations. Delays are represented by statistical distributions and the analysis step propagates distributions for arrival (required) times by applying the “add” and “maximum” (“subtract” and “minimum”) operations to these distributions. This approach requires significant resource allocation to characterizing the delay behavior for each process change.

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