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Solid-state image pickup device and clamp control method therefor

Solid-state image pickup device and clamp control method therefor description/claims

1. Field of the Invention

The present invention relates to a solid-state image pickup device for feeding back video signals picked up by an image sensor and applying the feedback video signals thus achieved as a control signal, and a clamp control method for the solid-state image pickup device.

2. Description of the Related Art

FIG. 15 is a block diagram showing an example of an analog front end processor (hereinafter referred to as “analog FE”) equipped to a conventional solid-state image pickup device.

An analog FE1 has a CDS (Correlated Double Sampling) circuit 3 for performing correlated double sampling processing on an input signal Vin input from an input terminal 2 by using plural sample hold (SH) circuits, an AGC (Automatic Gain Control) circuit 4 for controlling the gain of the CDS circuit 3, a low pass filter (LPF) circuit 5 for low-passing the output of the AGC circuit 4, a drive (DRV) amplifier 6 for amplifying the output of the LPF circuit 5 and outputting the amplified output from an output terminal 7, a clamp circuit 18 for clamping the output signal DRVout of the DRV amplifier 6 to a predetermined reference value. The output signal DRVout is clamped during a black reference signal period of an image pickup device by the clamp circuit 18.

The clamp circuit 18 has a feedback loop 18A for feeding back the output signal DRVout of the DRV amplifier 6, a switch 18B for opening/closing the feedback loop 18A on the basis of a clamp control signal CLPOB input from the external, and an OP amplifier 12 for comparing the voltage value of the output signal DRVout with a reference voltage value Vref based on a predetermined reference voltage source 11 and outputting the differential signal thereof. The AGC circuit 4 is controlled on the basis of the differential signal ΔVout from the OP amplifier 12 to clamp the output signal so that the voltage value of the output signal DRVout and the reference voltage value Vref are equal to each other.

A node 18C connected to an external feedback-loop capacitor 15 through an external connection terminal 14 of the analog FE1 is equipped between the switch 18B of the feedback loop 18A and the AGC circuit 4. Further, the OP amplifier 12 and the reference voltage source 11 are connected to a reference power source capacitance 9 through an external connection terminal 8 of the analog FE1. Further, the clamp control signal CLPOB is input from the external connection terminal 19.

IC constituting such an analog FE1 is usually used as a signal processing IC for the output signal of a solid-state image pickup device such as a CCD image sensor, or a CMOS image sensor.

The conventional CCD image sensor or the CMOS image sensor generally has a black reference signal at least one of a vertical blanking period and a horizontal blanking period, and sets the clamp control signal CLPOB input from the external to “ON” during a black reference signal output period at a frame period or a horizontal period and actuates the switch 18B of the feedback loop 18A so that the voltage value of the output signal DRVout and the reference voltage value Vref are equal to the same voltage. Accordingly, even when the black reference signal voltage of the input signal is varied, the output signal DRVout can be output on the basis of the constant reference voltage value Vref fixed at all times.

FIG. 16 is a block diagram showing an analog FE2 equipped to another conventional solid-state image pickup device. In FIG. 16, the common elements with FIG. 15 are represented by the same reference numerals.

The analog FE2 of FIG. 16 is designed so that the reference voltage source 11 of the clamp circuit 18 shown in FIG. 15 described above is equipped at the outside of IC (not shown), and the reference voltage value Vref is input from an external connection terminal 17.

The feedback loop 18A, the switch 18B, the OP amplifier 12, etc. of the clamp circuit 18 are equipped in IC. In place of the output of the DRV amplifier 6, the output of the LPF circuit 5 is used as a signal to be fed back as shown in FIG. 16.

This type of analog FE is used for a one-chip circuit containing not only the CDS function and the AGC function, but also an A/D (Analog-Digital Converter) function and a TG (Timing Generator) function of driving an image sensor. Further, a solid-state image pickup device such as CDD, or a CMOS image sensor which contains these functions therein is broadly used.

However, the conventional circuit construction described above has had a disadvantage that it is difficult to prevent the effect of noises contaminated from the power source voltage or GND.

FIG. 17 is a diagram showing an example of a noise voltage contaminated to the power source as described above, and the ordinate represents the noise voltage while the abscissa represents the frequency.

The output signal DRVout from the IC chip described above is delivered to a signal processing board (or signal processing IC) at the next stage, however, the problem of noise contamination from the signal processing board (or signal processing IC) exists.

As shown in FIG. 17, as noises contaminated into an image exist the 30 Hz noise corresponding to a frame frequency contaminated from the signal processing board (or signal processing IC) at the next stage, higher harmonic wave frequency noises of the 30 Hz noise, a 50 Hz noise contaminated from the power source and the higher harmonic wave frequency noises of the 50 Hz noise. Accordingly, it is required to suppress the noises contaminated from the power source and the noises contaminated from the signal processing board (or signal processing IC) at the next stage as described above.

Further, in order to prevent fluctuation of the external terminal voltage out of the feedback period, it has been needed to lead out at least one node 18C of the feedback loop 18A as an external terminal connection 14 and connect an element having a large capacitance value to the capacitor 15 described above (see FIG. 15).

This capacitance value is equal to a large value (about 0.1 μF to 10 μF), and thus a large part volume is needed. Therefore, it is difficult to miniaturize a camera system using such an IC chip as described above.

In view of the foregoing situation, the present invention has an object to provide a solid-state image pickup device which can suppress the effect of noises contaminated from a power source, an external circuit, etc. into a clamp circuit for clamping an output signal during a black reference signal period in an analog front end IC chip having a CDS function, an AGC function, etc., and simplify the construction of the IC chip, and a clamp control method for the solid-state image pickup device.

In order to attain the above object, according to the present invention, there is provided a solid-state image pickup device including an image sensor having a black reference signal during at least one of a vertical blanking period and a horizontal blanking period, a correlated double sampling circuit for removing noises from the output signal from the image sensor, a gain control amplifier for amplifying the output signal of the correlated double sampling circuit, and a clamp circuit for making the output value of the gain control amplifier corresponding to the period of the blank reference signal coincident with a predetermined reference value, wherein the clamp circuit has a feedback loop for performing feedback control on the gain control amplifier on the basis of the output signal, operating means for comparing the output signal output to the feedback loop with the reference value and outputting a clamp signal, a switch for opening/closing the feedback loop in accordance with the period of the black reference signal, and gain control means for controlling the gain of the clamp signal supplied to the gain control amplifier.

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