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Method for fabricating a semiconductor structure having heterogeneous crystalline orientations

Method for fabricating a semiconductor structure having heterogeneous crystalline orientations description/claims

The present invention relates, generally, to the fabrication of semiconductor layers having different crystalline orientations along a common surface and, more particularly, to methods for fabricating a semiconductor surface having heterogeneous crystalline orientations using epitaxial processes.

The trend in semiconductor process technology is toward higher speed devices that can be fabricated in substrates having heterogeneous structures. For example, silicon-on-insulator substrates have been developed that provide a thin surface layer upon which active devices are fabricated. Several fabrication techniques have been developed to provide substrates having a thin film overlying a buried insulating layer. Such process techniques include implantation of oxygen into a substrate known as “SIMOX” and implantation followed by fracturing and lift off, known as “SMARTCUT”. The object of substrate fabrication using processes such as SIMOX and SMARTCUT is to produce a very thin homogeneous layer overlying a buried insulating structure. While high speed devices can be formed in the homogeneous thin film, further refinement and substrate processing can lead to even higher speed devices.

Conventional silicon processing technology has developed to form metal-oxide-semiconductor (MOS) devices having both n-type and p-type conductivity. Such devices are commonly fabricated in integrated circuits employing complementary-metal-oxide-semiconductor (CMOS) technology. A wide variety of devices can beneficially employ CMOS technology, including RF analog devices, memory devices, microprocessor devices, and the like.

To improve the performance of n-type and p-type transistors, substrates are provided having heterogeneous crystalline orientations that are known to increase the carrier mobility of either an n-type transistor or a p-type transistor. For example, in silicon substrate technology, it is known that electron mobility is higher on silicon having a (100) or (001) crystalline orientation, while hole mobility is higher on a silicon surface having a (110) surface.

The fabrication of a substrate surface having differing crystalline orientations on the same surface requires advanced process technology and producing a defect-tree surface has prove problematic and expensive. In one such technique, silicon wafers are bonded together where one wafer has a (100) orientation and the other wafer has a (110) orientation. After bonding, the (110) wafer is masked and etched to expose portions of the underlying (100) wafer. Then, an epitaxial deposition process is carried out to grow (100) silicon on the exposed underlying wafer surface.

Another substrate fabrication process includes depositing dielectric layers on a silicon substrate having a (100) orientation. Then, silicon having a (110) orientation is deposited onto the dielectric layers. Next, an additional dielectric layer is formed over the (110) silicon and a resist pattern is form on the dielectric layer. The stack including the (110) silicon and adjacent dielectric layers is etched back to expose portions of the underlying (100) silicon surface. An epitaxial silicon deposition process is carried out to grow (100) silicon on the exposed portions of the underlying silicon surface.

While the existing substrate fabrication processes provide a substrate surface having a heterogeneous crystalline orientation, they require numerous processing steps that increase the possibility of contamination and require precise lithographic and etching techniques. Accordingly, a need existed for an improved method to fabricate semiconductor structures having heterogeneous crystalline orientation.

In one embodiment, a method for fabricating a semiconductor structure having heterogeneous crystalline orientations includes providing a first region including a semiconductor material having a first crystalline orientation. An epitaxial buffer is formed on the first semiconductor region and a second region of the semiconductor material is formed on the buffer layer. The second region of semiconductor material has a second crystalline orientation that differs from the first crystalline orientation.

In another embodiment, a method for fabricating a semiconductor layer includes providing a semiconductor substrate having a fist crystalline orientation. A first crystalline dielectric layer is formed on the semiconductor substrate, where the first crystalline dielectric layer has the same crystalline orientation as the semiconductor substrate. A second crystalline dielectric layer is formed on the first crystalline dielectric layer. A semiconductor region is formed on the second crystalline dielectric layer, where the semiconductor region has a second crystalline orientation different from the first crystalline orientation.

In yet another embodiment, a method for fabricating a semiconductor layer includes providing a semiconductor substrate having a first device region of a first conductivity type and a second device region of a second conductivity type, where the semiconductor substrate has a first crystalline orientation. A buffer is formed on at least the p-type device region and a semiconductor layer is formed on the buffer. The semiconductor layer has a second crystalline orientation different from the first crystalline orientation.

FIGS. 1-3 are cross-sectional views illustrating processing steps in accordance with an embodiment of the invention; and

FIG. 4 illustrates a semiconductor structure fabricated in accordance with an embodiment of the invention.

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