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Method and apparatus for normalizing thermal gradients over semiconductor chip designs

Method and apparatus for normalizing thermal gradients over semiconductor chip designs description/claims

This application is a continuation of U.S. patent application Ser. No. 11/215,783, filed Aug. 29, 2005, which is a continuation-in-part of U.S. patent application Ser. No. 10/979,957, field Nov. 3, 2004. In addition, application Ser. No. 11/215,783 claims the benefit of U.S. Provisional Patent Application No. 60/605,889, filed Aug. 30, 2004.

The present invention generally relates to semiconductor chip design, and more particularly relates to the thermal analysis of semiconductor chip designs.

Semiconductor chips typically comprise the bulk of the components in an electronic system. These semiconductor chips are also often the hottest part of the electronic system, and failure of the system can often be traced back to thermal overload on the chips. As such, thermal management is a critical parameter of semiconductor chip design.

FIG. 1 is a schematic diagram illustrating an exemplary semiconductor chip 100. As illustrated, the semiconductor chip 100 comprises one or more semiconductor devices 102a-102n (hereinafter collectively referred to as “semiconductor devices 102”), such as transistors, resistors, capacitors, diodes and the like deposited upon a substrate 104 and coupled via a plurality of wires or interconnects 106a-106n (hereinafter collectively referred to as “interconnects 106”). These semiconductor devices 102 and interconnects 106 share power, thereby causing a distribution of temperature values over the chip 100 that may range from 100 to 180 degrees Celsius in various regions of the chip 100.

In addition to large absolute temperatures, large variations in the thermal gradient over a semiconductor chip can cause the chip to fail in operation. Thus, accurate knowledge of the expected thermal gradient is critical in determining the layout of the chip. Unfortunately, though many methods exist for performing thermal analysis of semiconductor chips, such conventional methods typically fail to provide a complete or an entirely accurate picture of the chip's operating thermal gradient. For example, typical thermal analysis models attempt to solve the temperature on the chip substrate, but do not solve the temperature in a full three dimensions, e.g., using industry standards design, package and heat sink data. Moreover, most typical methods do not account for the sharing of power among semiconductor devices and interconnects, which distributes the heat field within the chip, as discussed above.

Therefore, there is a need in the art for a method and apparatus for normalizing thermal gradients over semiconductor chip designs.

A method and apparatus for normalizing thermal gradients over semiconductor chip designs is provided. One embodiment of a novel method for normalizing an expected thermal gradient includes determining a location of the thermal gradient in the semiconductor chip design and inserting at least one supplemental heat source into the semiconductor chip design such that the thermal gradient is normalized by heat dissipated by the supplemental heat source.

So that the manner in which the above recited embodiments of the invention are attained and can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to the embodiments thereof which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.

FIG. 1 is a schematic diagram illustrating an exemplary semiconductor chip;

FIG. 2 is a schematic diagram illustrating one implementation of a thermal analysis tool according to the present invention;

FIG. 3 is a flow diagram illustrating one embodiment of a method for performing three-dimensional thermal analysis of a semiconductor chip design according to the present invention;

FIG. 4 is a graph illustrating the change in value of transistor resistance for an exemplary negative channel metal oxide semiconductor as a function of the output transition voltage;

FIG. 5 is a flow diagram illustrating one embodiment of a method for normalizing thermal gradients over a semiconductor chip design, according to the present invention;

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