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Modulator driver circuit with selectable on-chip termination

Abstract: A method and apparatus to accommodate differing output loads without sacrificing impedance matching in an optical modulator driver. (end of abstract)


Agent: Kacvinsky LLC C/o Intellevate - Minneapolis, MN, US
Inventors: Mehdi Kazemi-Nia, Ivan I. Chen
USPTO Applicaton #: #20090041475 - Class: 398198 (USPTO)

Modulator driver circuit with selectable on-chip termination description/claims


The Patent Description & Claims data below is from USPTO Patent Application 20090041475, Modulator driver circuit with selectable on-chip termination.

Full Patent Description - Patent Application Claims  monitor keywords
BACKGROUND

A high speed optical communication system may use various methods to modulate an optical signal with data information for propagation along an optical transmission medium such as optical fiber. Optical modulators may use a driver circuit to provide an electrical signal corresponding to the data to be modulated. Impedance matching, where the maximum transfer of power from the driver circuit to the modulator, however, takes place when the source and load impedances (in this case driver and modulator impedances) are complex conjugates. Typically, drivers on separate chips have been employed to drive different output loads. These driver circuits, however, must support various output load values without sacrificing associated impedance matching. Consequently, there may be a need for improvements in impedance matching for optical modulator driver circuits while obviating the need for separate modulator chips and chipsets to drive various output loads.

BRIEF DESCRIPTION OF THE DRAWINGS

The subject matter regarded as embodiments is particularly pointed out and distinctly claimed in the concluding portion of the specification. The embodiments, however, both as to organization and method of operation, together with objects, features, and advantages thereof, may best be understood by reference to the following detailed description when read with the accompanying drawings in which:

FIG. 1 is a block diagram of a transceiver 110 utilized in high speed optical communication systems suitable for practicing one embodiment;

FIGS. 2A-2C schematically illustrate various driver circuits in accordance with one embodiment;

FIGS. 3A-3C schematically illustrate various driver circuits in accordance with one embodiment;

FIG. 4A illustrates a circuit for a 50 .OMEGA. load dual driver circuit in accordance with one embodiment; and

FIG. 4B illustrates a circuit for a 25 .OMEGA. load dual driver circuit in accordance with one embodiment.



Full Patent Description - Patent Application Claims
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Industry Class:
Optical communications

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