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Method of manufacturing a semiconductor integrated circuit device having a trench

Method of manufacturing a semiconductor integrated circuit device having a trench description/claims

This application is a Continuation application of application Ser. No. 11/189,833, filed Jul. 27, 2005, which is a Continuation application of application Ser. No. 10/919,432, filed Aug. 17, 2004, now U.S. Pat. No. 6,967,141, issued Nov. 22, 2005, which is a Divisional application of application Ser. No. 10/270,188, filed Oct. 15, 2002, now abandoned, which is a Divisional application of application Ser. No. 09/473,297, filed Dec. 28, 1999, the contents of which are incorporated herein by reference in their entirety. Application Ser. No. 09/473,297 has now issued as U.S. Pat. No. 6,544,839, on Apr. 8, 2003.

The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same; and, more specifically, the invention relates to an effective technology adapted to an element isolation structure for forming a fine MISFET (Metal Insulator Semiconductor Field Effect Transistor) and a method of manufacturing the same.

Although local oxidation of silicon (LOCOS) has been widely used as an element isolation technology in an LSI production process, the introduction of a new element isolation technology is being developed to facilitate the downsizing of a semiconductor element.

Shallow groove isolation (SGI) which is effected by burying an insulating film, such as a silicon oxide film, in a trench formed in a silicon substrate can (a) reduce the interval between, (b) easily control the thickness of an element isolating film and set a field reverse voltage, and (c) separate an anti-reflection layer from a diffusion layer and a channel region by striking different impurities into the side wall and the bottom of the trench. Therefore, it is more advantageous in securing sub-threshold characteristics and reducing a bonding leak and back-gate effect than the local oxidation of silicon.

A general method of forming an element isolation trench is as follows. A silicon substrate is first thermally oxidized to form a thin silicon oxide film on the surface, a silicon nitride film is formed on the silicon oxide film by chemical vapor deposition (CVD), and the silicon nitride film of an element isolation region is removed by dry etching using a photoresist film as a mask. Thereafter, the photoresist film is removed, a trench as deep as 350 to 400 nm is formed in the substrate by dry etching using the silicon nitride film as a mask, and the substrate is thermally oxidized to form a thin silicon oxide film on the inner wall of the trench. This silicon oxide film is formed to eliminate etching damage which occurs on the inner wall of the trench and to alleviate the stress of the silicon oxide film buried in the inside of the trench in a later step.

After a thick silicon oxide film is formed on the substrate containing the inside of the trench by CVD, the substrate is heated to finely densify the silicon oxide film buried in the inside of the trench. Thereafter, the silicon oxide film formed on the silicon nitride film is removed by chemical mechanical polishing (CMP) so that the silicon oxide film remains only in the inside of the trench, and the unnecessary silicon nitride film is removed by etching to complete an element isolation trench.

It is known that, in the above element isolation structure, a gate oxide film formed on the surface of the substrate of an active region is locally thin at the end portion (shoulder portion) of the active region and the field of gate voltage is concentrated upon this shoulder portion with the result of the occurrence of a phenomenon in which a drain current flows with a low gate voltage (may be called “kink characteristics” or “hump characteristics”). As a solution to this, a technology for rounding the shoulder portion of the active region is proposed.

For example, Japanese Patent Laid-open No. Sho 63-2371 indicates such a problem that, when a fine MISFET having a channel width of 1 μm or less is formed in the active region of the substrate surrounded by the above element isolation trench, it cannot be used as a device due to a reduction in threshold voltage (Vth), so-called “narrow channel effect”. This is because the shoulder portion of the active region has an angular cross section close to a right angle in the element isolation structure where an insulating film is buried in the inside of a trench formed in the substrate, whereby the field of the gate voltage is concentrated upon this region and a channel is formed with a low gate voltage.

The above publication discloses a technology for preventing a reduction in threshold voltage by forming a trench in the substrate, rounding the shoulder portion of the active region through wet oxidization at 950° C. and thickening the gate oxide film of the shoulder portion of the active region in order to suppress the above narrow channel effect.

Japanese Patent Laid-open No. Hei 2-260660 also discloses a technology for suppressing the concentration of the field of the gate voltage upon the shoulder portion of the active region by rounding the shoulder portion to prevent the occurrence of the above kink (hump) characteristics. In this publication, the shoulder portion of the active region is substantially rounded by the following method.

The element formation region of a semiconductor substrate is covered with a mask made of a laminate film consisting of an oxide film and an oxidation resistant film, and the substrate is thermally oxidized in this state to form an oxide film on the substrate of an element isolation region such that one end of the oxide film encroaches on the element formation region. Thereafter, the oxide film of the element isolation region is removed by wet etching using the above oxidation resistant film as a mask, a trench is formed in the substrate of the element isolation region by reactive ion etching using the above oxidation resistant film as a mask, the substrate is thermally oxidized to form a thermal oxide film on the inner wall of the trench, and the shoulder portion of the trench is rounded.

FIG. 30 is an enlarged view of the shoulder portion of the active region and therearound. A left part of the figure shows the substrate of the active region on the surface of which a gate oxide film 60 is formed. A right part of the figure shows an element isolation trench in which a silicon oxide film 61 is buried. Further, a gate electrode 62 which extends in right and left directions of the figure is formed on the top of the active region and the element isolation trench.

As shown in the figure, in the element isolation trench formed by burying the silicon oxide film 61 in the inside of a trench formed in the substrate, the surface of the silicon oxide film 61 is recessed downward in the vicinity of the active region. When the trench is formed in the substrate by etching using a silicon nitride film formed on the substrate of the active region as a mask, the silicon oxide film 61 is buried in the inside of the trench to flatten the surface, and the unnecessary silicon nitride film is removed by etching, a level difference corresponding to the thickness of the silicon nitride film is produced between the surface of the substrate of the active region and the surface of the silicon oxide film 61 buried in the trench. When the surface of the silicon oxide film 61 is wet etched with hydrofluoric acid to reduce this level difference, portions in contact with the silicon nitride film, that is, the top surface and side surface of the silicon oxide film 61 in the vicinity of the active region are exposed to hydrofluoric acid, whereby the amount of etching in that region is larger than that of the silicon oxide film 61 of a region spaced from the active region.

When the silicon oxide film 61 in the vicinity of’ the active region is recessed downward as described above, an end portion of the gate oxide film 60 formed on the surface of the substrate of the shoulder portion of the active region reaches part of the side wall of the element isolation trench. However, as it is difficult to strike an impurity for forming a channel into the side wall of the element isolation trench, the concentration of an impurity in this region becomes lower than the concentration of an impurity in a flat portion of the active region. As a result, when voltage is applied to the gate electrode, a sub-channel is formed in the shoulder portion of the active region before a channel is formed in the flat portion of the active region, resulting in a reduction in threshold voltage. Particularly, when the gate width is reduced along with a reduction in the width of a MISFET, the influence of the sub-channel becomes marked and a reduction in threshold voltage becomes large. This phenomenon represents a very serious problem for a surface channel type MISFET in which a gate electrode is formed from n type polycrystal silicon.

As means of preventing the above reduction in threshold voltage, it is conceivable to increase the dose of an impurity for the formation of a channel so as to compensate for a reduction in the concentration of the impurity in the shoulder portion of the active region. However, since the concentration of the impurity in the substrate increases in this method, in the case of a dynamic random access memory (DRAM), for example, the field strength becomes high in the vicinity of the semiconductor region of a storage node and a leakage current grows, thereby causing a reduction in refresh characteristics and an increase in the parasitic capacity of a bit line.

When a fine MISFET is to be thus formed in the active region of the substrate surrounded by the element isolation trench, a reduction in threshold voltage cannot be prevented by rounding the shoulder portion of the active region and some measure must be taken to suppress the formation of a sub-channel in the shoulder portion of the active region as described above.

It is an object of the present invention to provide a technology for promoting a reduction in the size of a MISFET by optimizing the shape of an element isolation trench.

It is another object of the present invention to provide a technology for improving the refresh characteristics of a DRAM whose size has been reduced.

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