Site News  |   Monitor Keywords  |   Monitor Archive  |   Organizer  |   Account Info  |

Hermetic pacakging and method of manufacture and use therefore

Hermetic pacakging and method of manufacture and use therefore description/claims

This application is a divisional of application Ser. No. 11/113,545, filed Apr. 25, 2005 claiming This claims the benefit of the following provisional patents: attorney's docket number JSF02-0009 filed Jun. 1, 2004 (APPL No. 60/575,586), attorney's docket number JSF02-0010 filed Sep. 7, 2004 (APPL No. 60/607,723), and attorney's docket number JSF02-0011 filed Nov. 8, 2004 entitled, “METHOD OF MANUFACTURING HERMETIC PACKAGING” (APPL NO TBD).

Hermetic packaging, which provides tightly sealed cavities, has been used to protect many MEMS (micorelectromechnaical systems), such as optical, RF (radio frequency) and sensor devices, against moisture and other corrosive gases from seeping in, or to keep under controlled atmosphere. Specific examples include DLP™, bolometer, accelerometers and gyroscope. Wafer-level packaging offers advantages for packaging of cavities brings the cost advantage of simultaneously sealing an entire wafer of cavities. This eliminates the manufacturing inefficiencies and the costs of individual “pump down and pinch off” for archaic metal or ceramic packages. These potential cavity package advantages have sparked many development efforts for wafer-scale hermetic cavity packaging. The earliest cavity wafer-level packaging to be produced in large quantities were for protecting MEMS devices with moving surface elements. Millions of automotive airbag systems are today controlled by MEMS accelerometers residing in hermetic cavity wafer-level packages. More recently, cavity non-hermetic wafer-level packaging support high-volume consumer applications, such as digital cameras. Controlled-atmosphere hermetic cavity wafer-level packaging are currently being offered for MEMS RF switches. Further developments aim at size, weight and cost reductions for limited-lifetime products, or at economically meeting the more stringent requirements of high-performance, long-lifetime MEMS, optical devices and sensors.

Since cavity wafer-level packaging by their nature are generally precluded from adding layers over the active devices on the wafer surface, cavity packages are created either by bonding a second wafer with pre-formed cavities over the device wafer (wafer stacking) or by dicing the second wafer and bonding the individual cavity chips onto the device wafer (chip-on-wafer).

The present invention relates to manufacturing hermetic packaging cavities at the wafer level by wafer bonding and forming enclosures that is impervious to moisture or ambient gas. One approach to fabricating a wafer-level cavity package is to use epoxy to bond a cap wafer with a stenciled wafer for forming open cavities on one side first. Then this wafer is likewise bonded and sealed to the substrate wafer that contains MEMS devices (such as DLP™, accelerometers), thereby sealing numerous MEMS devices on the substrate wafer in enclosure cavities. This approach is very simple and cost effective. However, because of the permeability and possible out-gassing of the epoxy seals, the package is classified as non-hermetic. Another approach is to enclose the MEMS devices in deposited film using a sacrificial layer as temporary support, which is subsequently removed by etching through small holes in the deposited films, which is in turn sealed with deposited film. This approach is only suitable for very small devices because the films are much thinner than the cap wafers made from bulk material.

An embodiment of the present invention provides a method for manufacturing hermetic packages on wafer scale. It may use surface micromachining technique to fabricate the packaging. The technique may employ polymer bonding and thin film deposition to package MEMS or other devices under controlled atmosphere. They are impervious to moisture and gases and may be fabricated at low temperatures.

FIGS. 1 through 9 depict cross-sectional side views and their associated perspective views, showing a particular portion of a microstructure during specific phases of the wafer-level hermetic or vacuum packaging process for a MEMS device;

FIGS. 10 through 15 depict cross-sectional side views and their associated perspective views, showing a particular portion of a microstructure during a specific phase of the wafer-level hermetic or vacuum packaging process for a MEMS device;

FIG. 16 depicts cross-sectional side view, showing a particular portion of a microstructure during specific phases of the wafer-level packaging process for a MEMS device;

FIG. 17 depicts top views, showing a particular portion of a microstructure during specific phases of the wafer-level packaging process for a MEMS device.

A method and system for cavity packaging MEMS devices, such as the DLP™ (digital light processor) on wafer scale in hermetic or vacuum seal is described herein. The processes of the wafer-level packaging begin during or after the final phase of the MEMS device fabrication process, and before the wafer are diced into separate chips. Referring now to FIGS. 1 to 9, there is a depicted cross-sectional view showing a particular portion of a microstructure during specific phases of the packaging process for the exemplary MEMS device. The dimensions are not shown to scale.

• Provisional Patent
• Utility Patent

• What Is a Patent?
• What Is a Trademark or Servicemark?
• What Is a Copyright?
• Patent Laws