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01/22/09 - USPTO Class 716 |  1 views | #20090024969 | Prev - Next | About this Page  716 rss/xml feed  monitor keywords

Semiconductor chip design having thermal awareness across multiple sub-system domains

USPTO Application #: 20090024969
Title: Semiconductor chip design having thermal awareness across multiple sub-system domains
Abstract: A thermally aware design automation suite integrates system-level thermal awareness into the design of semiconductor chips. A thermal analysis engine performs fine-grain thermal simulations of the semiconductor chip based on thermal models and boundary conditions for all thermally significant structures in the chip and the adjacent system that impact the temperature of the semiconductor chip. The thermally aware design automation suite uses the simulations of the thermal analysis engine to repair or otherwise modify the thermally significant structures to equalize temperature variations across the chip, impose specified design assertions on selected portions of the chip, and verify overall chip performance and reliability over designated operating ranges and manufacturing variations. The thermally significant structures are introduced or modified via one or more of: change in number, change in location, and change in material properties. (end of abstract)



Agent: Walstein Bennett Smith Iii - Georgetown, TX, US
Inventor: Rajit Chandra
USPTO Applicaton #: 20090024969 - Class: 716 5 (USPTO)

Semiconductor chip design having thermal awareness across multiple sub-system domains description/claims


The Patent Description & Claims data below is from USPTO Patent Application 20090024969, Semiconductor chip design having thermal awareness across multiple sub-system domains.

Brief Patent Description - Full Patent Description - Patent Application Claims
  monitor keywords CROSS REFERENCE TO RELATED APPLICATIONS

Priority benefit claims for this application are made in the accompanying Application Data Sheet (if any). To the extent permitted by the type of the instant application, this application incorporates by reference for all purposes the following applications, which are all owned by the owner of the instant application:

U.S. Application Serial No. ______ (Docket No. GDA.2005.08NP) filed herewith, by Rajit Chandra, and entitled Method and Apparatus for Thermally Aware Design Improvement;

U.S. Application Serial No. ______ (Docket No. GDA.2005.09NP) filed herewith, by Rajit Chandra, and entitled Method and Apparatus for Generating and Using Thermal Test Vectors;

U.S. Provisional Application Ser. No. 60/751,376 (Docket No. GDA.2005.23) filed Dec. 17, 2005, by Rajit Chandra, et al., and entitled Semiconductor Chip Design Having Thermal Awareness Across Multiple Sub-System Domains;

U.S. Provisional Application Ser. No. 60/734,372 (Docket No. GDA.2005.24) filed Nov. 7, 2005, by Rajit Chandra, et al., and entitled Efficient Full-Chip Thermal Modeling and Analysis;

U.S. Provisional Application Ser. No. 60/718,138 (Docket No. GDA.2005.22) filed Sep. 16, 2005, by Rajit Chandra, and entitled Method and Apparatus for Temperature Assertion Based IC Design;

U.S. application Ser. No. 11/215,783 (Docket No. GRAD/011) filed Aug. 29, 2005, by Rajit Chandra, and entitled Method and Apparatus for Normalizing Thermal Gradients Over Semiconductor Chip Designs;

U.S. application Ser. No. 11/198,467 (Docket No. GRAD/009) filed Aug. 5, 2005, by Rajit Chandra, and entitled Method and Apparatus for Optimizing Thermal Management Systems Performance Using Full-Chip Thermal Analysis of Semiconductor Chip Designs;

U.S. application Ser. No. 11/198,470 (Docket No. GRAD/010) filed Aug. 5, 2005, by Rajit Chandra, and entitled Method and Apparatus for Using Full-Chip Thermal Analysis of Semiconductor Chip Designs to Compute Thermal Conductance;

U.S. application Ser. No. 11/180,353 (Docket No. GRAD/006) filed Jul. 13, 2005, by Ping Li, et al., and entitled Method and Apparatus for Thermal Modeling and Analysis of Semiconductor Chip Designs;

U.S. Provisional Application Ser. No. 60/689,592 (Docket No. GDA.2005.20) filed Jun. 10, 2005, by Rajit Chandra, and entitled Temperature-Aware Design Methodology;

U.S. Application Ser. No. 11/078,047 (Docket No. GRAD/003) filed Mar. 11, 2005, by Rajit Chandra, et al., and entitled Method and Apparatus for Thermal Testing of Semiconductor Chip Designs;

U.S. Provisional Application Ser. No. 60/658,323 (Docket No. GDA.2005.09) filed Mar. 3, 2005, by Rajit Chandra, and entitled Method and Apparatus for Generating and Using Thermal Test Vectors;

U.S. Provisional Application Ser. No. 60/658,324 (Docket No. GDA.2005.08) filed Mar. 3, 2005, by Rajit Chandra, and entitled Method and Apparatus for Thermally Aware Design Improvement;

U.S. application Ser. No. 11/039,737 (Docket No. GRAD/007) filed Jan. 20, 2005, by Rajit Chandra, and entitled Method and Apparatus for Retrofitting Semiconductor Chip Performance Analysis Tools with Full-Chip Thermal Analysis Capabilities; and

U.S. application Ser. No. 10/979,957 (Docket No. GRAD/012) filed Nov. 3, 2004, by Rajit Chandra, and entitled Method and Apparatus for Full-Chip Thermal Analysis of Semiconductor Chip Designs.

BACKGROUND

1. Field

Advancements in semiconductor chip design are needed to provide improvements in performance, efficiency, and utility of use.

2. Related Art



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