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Dual-gate device and method

Dual-gate device and method description/claims

The present application is a division of U.S. patent application Ser. No. 11/548,231 filed on Oct. 10, 2006, which is incorporated herein by reference. Also, the subject matter of the present patent application is related to (a) U.S. patent application Ser. No. 11/000,114 (“the '114 application”), entitled “Dual-Gate Device and Method,” filed on Nov. 29, 2004 and to (b) U.S. patent application Ser. No. 11/197,462 (“the '462 application”), entitled “Dual-Gate Device and Method,” filed on Aug. 3, 2005. Disclosures of the '114 and '462 applications are hereby incorporated by reference in their entireties.

1. Field of the Invention

The present invention relates to a semiconductor device. In particular, it relates to a semiconductor device having dual gate electrodes.

2. Discussion of the Related Art

Dual-gate semiconductor devices have been used as non-volatile memory devices. For example, K. Yanagidaira et al (“Yanagidaira's paper”), IEEE Electron Device Letters, vol. 26, pp. 473-475, July 2005, report a dual-gate silicon nanocrystal memory where electric charge stored on one side of the dual-gate device would strongly affect the threshold voltage of the device on the other side of the dual-gate device. Dual-gate semiconductor devices have also been used in NAND-type semiconductor non-volatile memory (“flash memory”) cells. For example, U.S. Pat. No. 6,054,734 to Aozasa et al. (“the '734 patent”), entitled “Non-volatile Memory Cell Having Dual-gate Electrodes,” filed on Nov. 5, 1997 and issued on Apr. 25, 2000, discloses that a dual-gate approach allows reduced read disturb and better control over threshold voltage distributions in the programmed and erased states as the minimum feature size shrinks.

FIG. 1 reproduces FIG. 4 of the '734 patent, which illustrates a dual-gate semiconductor device in a memory cell of the prior art. As shown in FIG. 1, region 24 is a supporting substrate (e.g., a silicon wafer), region 26 is an insulating layer separating the dual-gate device from the supporting substrate. Region 36 is a gate electrode of the first of two devices in the dual-gate device. Region 32 is the charge-storing gate dielectric layer of the first device. In one embodiment disclosed in the '734 patent, dielectric region 32 is described as a composite layer consisting of a layer of silicon nitride sandwiched between two oxide layers. Such a composite layer (often referred to as “ONO”) stores electric charge. Gate dielectric region 32 separates semiconductor channel region 30 from gate electrode region 36. The second gate electrode 38, which is the gate electrode for the second device, is separated from layer 30 by gate dielectric layer 34. Dielectric layer 34 does not store charge. Interconnecting layers 44 and 46 connect source and drain regions 40 and 42 to other circuitry.

As mentioned above, dual-gate memory cell 22 comprises a memory device having first gate electrode 36 and a non-memory device having second gate electrode 38. The memory device and the non-memory device are field effect devices. In a field effect device, when a voltage applied to a gate electrode is greater in magnitude than a “threshold” voltage (relative to a source electrode), a conducting channel forms between the source electrode and a drain electrode. By placing electric charge between the gate electrode and the channel, this threshold voltage can be changed as a function of the stored charge. In the dual-gate device of FIG. 1, electric charge trapped in gate dielectric 32 affects the threshold voltages of both the memory device and the non-memory device. Such an effect results from the very close electrical interaction between the memory device and the non-memory device. In particular, to calculate the thickness of channel region 30, the '734 patent assumes that this semiconductor channel region is isotropic and monocrystalline. The amount of electric charge trapped in dielectric 32 is changed by programming and erasing operations effectuated by applying predetermined voltage levels on gate electrode 36 relative to the voltages in the source and drain regions 40 and 42.

FIG. 2 reproduces FIG. 17 of the '734 patent, which illustrates dual-gate semiconductor memory cells in a NAND configuration. As shown in FIG. 2, non-volatile semiconductor memory device 202 comprises eight serially-connected dual-gate memory devices, each formed using the single dual-gate memory cell 22 of FIG. 1. Insulating layer 206 isolates the dual-gate memory devices, MN1 through to MN8, from supporting substrate 204. Each dual-gate memory device in FIG. 2 consists of first gate electrode 216, which is separated from channel region 210 by gate dielectric layer 212 formed as an ONO film. Each dual-gate device further comprises second gate electrode 218, which is separated from channel region 210 by gate dielectric layer 214. Similar to dielectric film 32 in dual-gate memory cell 22 of FIG. 1, gate dielectric layer 212 is the gate dielectric layer that stores electric charge. FIG. 2's NAND configuration illustrates that source and drain regions 220 and 222, which are self-aligned to the second gate electrodes 218 by ion implantation, are used between serially-connected adjoining dual-gate devices.

The '734 patent teaches that the non-memory device in a dual-gate structure is used to read the presence or absence of charge in the corresponding memory device of the same dual-gate structure. For the non-memory device to detect the charge in the memory device, the thickness of channel region 210 (FIG. 2) is chosen to allow the electric field at one surface to influence the other surface. One method to achieve this effect is to allow one surface to be uniformly within the depletion region of the other surface, when a selected voltage is applied to the source electrode of the dual-gate device. Such a close electrical interaction means that the charge stored in gate dielectric 212 in FIG. 2 affects the threshold voltage of the non-memory device, which is measured by the voltage required to be applied to gate electrode 218 relative to either source electrode 220 or 222 to allow an electric current to flow through channel region 210.

The '734 patent further teaches that the memory device of the dual-gate device is programmed by applying a predetermined voltage to memory gate electrodes 216 through other memory devices, while the non-memory devices play no part in this programming operation. The NAND non-volatile memory of FIG. 2 has several disadvantages associated with it.

First, the requirement that the charge stored in the gate dielectric of the memory device affect the threshold voltage of the associated non-memory device in the dual-gate device ensures that strong electrical interaction exists between these two devices. This approach is taken in both the '734 patent and Yanagidaira's paper. Furthermore, using crystalline silicon in FIG. 2's channel region 210 ensures that this strong electrical interaction is uniform across the whole surface of each device's channel region. The method for reading a cell, as taught in the '734 patent, requires a current to pass through the channel region near its surface adjacent to the non-memory devices in the NAND string. Using this current to determine the actual threshold voltage of the device being read is difficult, as such a determination depends on being able to discriminate a current from a base current level that is affected by the programmed and erased states of all other memory cells in the string. This method is made even more challenging by the small difference in threshold voltages between the programmed and the erased state of a device, due to the relatively great distance over which the stored electric charge must act to affect these threshold voltages.

The strong, uniform electrical interaction between the non-memory device and its associated memory device also results in read disturb in the memory cells in the NAND serial string every time a single cell is read. This read disturb results from a change in the stored charge in each memory cell as a result of applying the read voltages to all non-memory gate electrodes of the NAND string.

A further disadvantage of the structure taught in '734 patent stems from the requirement that the memory device is programmed through other memory devices in the NAND string. Because of this requirement, each gate electrode of the memory devices between the bit line contact (e.g., bit line contact 224 in FIG. 2) and the selected memory device (i.e., the memory device to be programmed) must have a large applied voltage relative to the bit line contact voltage to ensure good electrical connection between the bit line contact and the inverted channel of the selected memory device. This “program pass voltage” is lower than the program voltage applied to the gate electrode of the selected memory device, but the program pass voltage can still lead to a serious program disturb sufficient, after repetitive application, to change the amount of electric charge in the unselected memory devices.

Other disadvantages of the approach used in the '734 patent are discussed in the '114 and '462 applications and are not repeated here for brevity.

In the '734 patent, the channel silicon thickness is calculated on the assumption that the channel semiconductor is fully monocrystalline and that depletion region thicknesses are determined by the dopant concentration in the channel. The principles for determining these thicknesses may be found, for example, in the article “Threshold Voltage of Thin-Film Silicon-on-Insulator (SOI) MOSFET's” (“the Lim Article”), by Lim and Fossum, published in IEEE Trans. Elect. Dev., vol. 30, no. 10 (October 1983), pp. 1244-1251. According the Lim Article, to provide the electrical interaction necessary for allowing the programmed state of the memory device to be read from the non-memory device, the thickness d of the semiconductor material for forming conducting channels of the memory and non-memory devices is given by:

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