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Image sensor pixel having photodiode with indium pinning layer

Image sensor pixel having photodiode with indium pinning layer description/claims

This application is a divisional of U.S. application Ser. No. 11/004,246 filed Dec. 3, 2004, now pending, entitled “Image Sensor Pixel Having Photodiode with Indium Pinning Layer,” which is hereby incorporated by reference.

The present invention relates to image sensors, and more particularly, to an image sensor that uses pixels with a photodiode having an indium surface dopant that forms a p+ pinning layer.

Image sensors have become ubiquitous. They are widely used in digital still cameras, cellular phones, security cameras, medical, automobile, and other applications. The technology used to manufacture image sensors, and in particular CMOS image sensors, has continued to advance at great pace. For example, the demands of higher resolution and lower power consumption have encouraged the further miniaturization and integration of the image sensor.

As the pixels become smaller, the surface area that can receive incident light is also reduced. The pixel typically has a light-sensing element, such as a photodiode, which receives incident light and produces a signal in relation to the amount of incident light. Thus, as the pixel area (and thus the photodiode area) decreases, the well capacity of the photodiode also becomes smaller.

One prior art structure of a photodiode that has enhanced well capacity comprises a shallow N− layer in a P-type region or substrate. A P+ pinning layer is then formed over the shallow N− layer. The P+ pinning layer is universally formed by implanting boron, because of boron's relatively good solid solubility.

This structure is known as a pinned photodiode and has relatively high well capacity, but sometimes at the expense of “dark current” performance and excess “hot pixel” defects. Further, because of the statistical nature of dopant implantation, the local concentration of an implanted dopant, such as the dopant for the N− layer, may vary spacially. In some cases, it is probable that a higher than average number of n-type ions are implanted near the silicon surface. This generates a local n-type region that punches into the surface P+ pinning region and can result in a local increase in dark current and hot pixel defect density.

FIG. 1 is a combination cross-sectional and schematic diagram of a prior art four transistor (4T) pixel which shows in detail a photodiode formed in a substrate.

FIGS. 2-6 are cross-sectional diagrams showing a method of making a photodiode and pixel in accordance with the present invention.

In the following description, numerous specific details are provided in order to give a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that the invention may be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well known structures, materials, or operations are not shown or described in order to avoid obscuring aspects of the invention.

Referenced throughout the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment and included in at least one embodiment of the present invention. Thus, the appearances of the phrase “in one embodiment” or “in an embodiment” in various places throughout the specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

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